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11. 发明授权

US06331943B1 MTJ MRAM series-parallel architecture 失效
标题翻译： MTJ MRAM系列并行架构
公开(公告)号：US06331943B1
公开(公告)日：2001-12-18
申请号：US09649117
申请日：2000-08-28
申请人： Peter K. Naji , Mark DeHerrera , Mark Durlam
发明人： Peter K. Naji , Mark DeHerrera , Mark Durlam
IPC分类号： G11C1100
CPC分类号： H01L27/228 , G11C11/15
摘要： Magnetic tunnel junction random access memory architecture in which an array of memory cells is arranged in rows and columns and each memory cell includes a magnetic tunnel junction and a control transistor connected in parallel. A control line is connected to the gate of each control transistor in a row of control transistors and a metal programming line extending adjacent to each magnetic tunnel junction is connected to the control line in spaced apart intervals by vias. Further, groups of memory cells in each column are connected in series to form local bit lines which are connected in parallel to global bit lines. The series-parallel configuration is read using a centrally located column to provide a reference signal and data from columns on each side of the reference column is compared to the reference signal or two columns in proximity are differentially compared.
摘要翻译：磁性隧道结随机存取存储器结构，其中存储器单元阵列以行和列排列，并且每个存储单元包括并行连接的磁性隧道结和控制晶体管。控制线连接到一排控制晶体管中的每个控制晶体管的栅极，并且与每个磁性隧道结相邻的金属编程线通过通孔以间隔开的间隔连接到控制线。此外，每列中的存储单元组被串联连接以形成与全局位线并行连接的局部位线。使用位于中心的列来读取串并联配置以提供参考信号，并且将参考列的每一侧的列中的数据与参考信号进行比较或差异地比较两个接近的列。

12. 发明授权

US5831920A GMR device having a sense amplifier protected by a circuit for dissipating electric charges 失效
标题翻译： GMR器件具有由用于耗散电荷的电路保护的读出放大器
公开(公告)号：US5831920A
公开(公告)日：1998-11-03
申请号：US949605
申请日：1997-10-14
申请人： Eugene Chen , Saied N. Tehrani , Mark Durlam , Peter K. Naji
发明人： Eugene Chen , Saied N. Tehrani , Mark Durlam , Peter K. Naji
IPC分类号： G11C11/16 , G11C7/00
CPC分类号： G11C11/16
摘要： A new and improved magnetic device is provided for memories and sensors. A magnetic random access memory (MRAM) device (20) includes a storage element (21) for magnetically storing states and an amplifier (25) for sensing the states stored in the storage element. A circuit (27) for dissipating electrical charges are coupled to inputs (23,24) of the amplifier (25) to discharge electrical charges applied to the inputs (23,24) of the amplifier (25). The charge dissipating circuit (27) includes junctions (271-274) which are typically connected in series between power (255) and common (257) lines. Electric charges applied to the inputs (23,24) of the amplifier (25) is discharged through the junctions (271-274).
摘要翻译：为存储器和传感器提供了一种新的改进的磁性器件。磁性随机存取存储器（MRAM）装置（20）包括用于磁存储状态的存储元件（21）和用于感测存储在存储元件中的状态的放大器（25）。用于耗散电荷的电路（27）耦合到放大器（25）的输入（23,24），以放电施加到放大器（25）的输入端（23,24）的电荷。电荷消耗电路（27）包括通常在功率（255）和公共（257）线之间串联连接的结（271-274）。施加到放大器（25）的输入端（23,24）的电荷通过接点（271-274）放电。

13. 发明申请

US20140321198A1 Memory Devices and Related Methods 有权
标题翻译：内存设备及相关方法
公开(公告)号：US20140321198A1
公开(公告)日：2014-10-30
申请号：US14325675
申请日：2014-07-08
申请人： Peter K. Naji
发明人： Peter K. Naji
IPC分类号： G11C13/00 , G11C11/16
CPC分类号： G11C13/0021 , G11C11/165 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C11/5642 , G11C13/0002 , G11C13/004 , G11C27/005
摘要： A resistive memory device. Implementations may include an array of memory cells including resistive memory elements which are coupled to isolation transistors and which may include a magnetic tunnel junction. A decoder decodes input address information to select a row of the array. A binarizer coupled to the memory array assigns binary weights to outputs of the memory array output through bit lines coupled to the memory cells. A summer sums the binary weighted outputs, and a quantizer generates an output digital code corresponding to data stored in a plurality of memory cells during a prior program cycle. The outputs of the memory array may be currents or voltages. In implementations multiple arrays of memory cells may be utilized and their respective outputs combined to form higher bit outputs, such as eight bit, twelve bit, sixteen bit, and so forth.
摘要翻译：电阻式存储器件。实施方案可以包括存储单元的阵列，包括耦合到隔离晶体管并且可以包括磁性隧道结的电阻性存储器元件。解码器解码输入地址信息以选择阵列的一行。耦合到存储器阵列的二进制化器通过耦合到存储器单元的位线将二进制权重分配给存储器阵列输出的输出。夏季对二进制加权输出求和，并且量化器在先前的程序周期期间生成对应于存储在多个存储单元中的数据的输出数字代码。存储器阵列的输出可以是电流或电压。在实现中，可以使用多个存储器单元阵列，并且它们各自的输出组合以形成较高位输出，例如8位，12位，16位等等。

14. 发明授权

US06552927B2 MRAM architecture and system 失效
公开(公告)号：US06552927B2
公开(公告)日：2003-04-22
申请号：US10141161
申请日：2002-05-08
申请人： Peter K. Naji
发明人： Peter K. Naji
IPC分类号： G11C700
CPC分类号： G11C11/16 , G11C11/1657
摘要： A magnetoresistive memory fabricated on a common substrate. The memory including first and second spaced apart magnetoresistive memory arrays each including a plurality of MTJ memory cells arranged in rows and columns and a plurality of word/digit lines associated with the rows of magnetoresistive memory cells of each of the arrays. Switching circuitry is positioned on the substrate between the first and second arrays and designed to select a word/digit line in one of the first and second arrays. A current source is positioned on the substrate adjacent and coupled to the switching circuitry for supplying programming current to the selected word/digit line.

15. 发明授权

US06512689B1 MRAM without isolation devices 失效
标题翻译： MRAM无隔离设备
公开(公告)号：US06512689B1
公开(公告)日：2003-01-28
申请号：US10051646
申请日：2002-01-18
申请人： Peter K. Naji , Mark A. Durlam , Saied N. Tehrani
发明人： Peter K. Naji , Mark A. Durlam , Saied N. Tehrani
IPC分类号： G11C1100
CPC分类号： G11C7/14 , G11C11/15
摘要： A magnetoresistive random access memory architecture free of isolation devices includes a plurality of data columns of non-volatile magnetoresistive elements. A reference column includes non-volatile magnetoresistive elements positioned adjacent to the data column. Each column is connected to a current conveyor. A selected data current conveyor and the reference current conveyor are connected to inputs of a differential amplifier for differentially comparing a data voltage to a reference voltage. The current conveyors are connected directly to the ends of the data and reference bitlines. This specific arrangement allows the current conveyors to be clamped to the same voltage which reduces or removes sneak circuits to substantially reduce leakage currents.
摘要翻译：没有隔离装置的磁阻随机存取存储器架构包括多个非易失性磁阻元件的数据列。参考柱包括与数据列相邻定位的非易失性磁阻元件。每列连接到当前输送机。选择的数据流传输器和参考电流传输器连接到差分放大器的输入端，用于将数据电压与参考电压进行差分比较。目前的输送机直接连接到数据和参考位线的末端。这种特定的布置允许当前输送机被夹紧到相同的电压，这减少或去除潜行电路以显着减少泄漏电流。

16. 发明授权

US06365419B1 High density MRAM cell array 失效
标题翻译：高密度MRAM单元阵列
公开(公告)号：US06365419B1
公开(公告)日：2002-04-02
申请号：US09649114
申请日：2000-08-28
申请人： Mark Durlam , Mark DeHerrera , Eugene Chen , Saied Tehrani , Gloria Kerszykowski , Peter K. Naji , Jon Slaughter , Kelly W. Kyler
发明人： Mark Durlam , Mark DeHerrera , Eugene Chen , Saied Tehrani , Gloria Kerszykowski , Peter K. Naji , Jon Slaughter , Kelly W. Kyler
IPC分类号： H01L2100
CPC分类号： H01L27/228 , B82Y10/00 , H01L43/12
摘要： A method of fabricating an MRAM cell includes providing an isolation transistor on a semiconductor substrate and forming an interconnect stack on the substrate in communication with one terminal of the transistor. A via is formed on the upper end of the stack so as to extend from a position below the digit line to a position above the digit line. The via also extends above the upper surface of a dielectric layer to provide an alignment key. A MTJ memory cell is positioned on the upper surface in contact with the via, and the ends of a free layer of magnetic material are spaced from the ends of a pinned edge of magnetic material by using sidewall spacers and selective etching.
摘要翻译：制造MRAM单元的方法包括在半导体衬底上提供隔离晶体管，并在衬底上形成与晶体管的一个端子连通的互连叠层。通孔形成在堆叠的上端，以从数字线下方的位置延伸到数字线上方的位置。通孔也延伸到电介质层的上表面之上，以提供对准键。 MTJ存储单元位于与通孔接触的上表面上，并且通过使用侧壁间隔件和选择性蚀刻，磁性材料的自由层的端部与磁性材料的被钉扎边缘的端部间隔开。

17. 发明授权

US06278631B1 Magnetic random access memory array divided into a plurality of memory banks 有权
标题翻译：磁性随机存取存储器阵列分为多个存储体
公开(公告)号：US06278631B1
公开(公告)日：2001-08-21
申请号：US09568822
申请日：2000-05-10
申请人： Peter K. Naji
发明人： Peter K. Naji
IPC分类号： G11C1100
CPC分类号： G11C11/15 , G11C11/16
摘要： An MRAM device has a new type of memory bank (10) that includes bit lines (21-24), a reference line (27) and digit lines (25, 26), on intersections of bit lines and digit lines a plurality of magnetic memory cells (15-18) are arrayed. Bit lines are formed on both sides of the reference line on a substrate. Since each bit line is fabricated closely to the reference line, each cell has substantially the same hysteresis characteristics, which allow the MRAM device to provide a steady operation mode.
摘要翻译：一种MRAM设备具有一种新型的存储体（10），其包括位线（21-24），参考线（27）和数字线（25,26），位线和数字线的交点具有多个磁存储单元（15-18）排列。位线形成在基板的基准线的两侧。由于每个位线与参考线紧密地制造，所以每个单元具有基本上相同的磁滞特性，这允许MRAM器件提供稳定的工作模式。

18. 发明授权

US5946227A Magnetoresistive random access memory with shared word and digit lines 失效
标题翻译：具有共享字和数字线的磁阻随机存取存储器
公开(公告)号：US5946227A
公开(公告)日：1999-08-31
申请号：US118977
申请日：1998-07-20
申请人： Peter K. Naji
发明人： Peter K. Naji
IPC分类号： G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/00
CPC分类号： G11C11/16 , G11C11/15
摘要： A high speed and high density magnetoresistive random access memory (MRAM) device (30) is provided. The MRAM device employs a poly-silicon word line (39a) that saves wiring space. Further, the word line is connected to a digit line (38a) by a connecting line (44a) which reduces a electrical resistance between transistors (43a) and (40a). Arrangement of the connecting line reduces a transmission time from a digit current control (33a) to transistor (43a) and greatly improves a memory cycle time.
摘要翻译：提供了一种高速和高密度磁阻随机存取存储器（MRAM）装置（30）。 MRAM器件采用节省布线空间的多晶硅字线（39a）。此外，字线通过减少晶体管（43a）和（40a）之间的电阻的连接线（44a）连接到数字线（38a）。连接线的布置减少了从数字电流控制（33a）到晶体管（43a）的传输时间，并且极大地改善了存储器周期时间。

19. 发明授权

US06609174B1 Embedded MRAMs including dual read ports 有权
标题翻译：嵌入式MRAM包括双重读取端口
公开(公告)号：US06609174B1
公开(公告)日：2003-08-19
申请号：US09420122
申请日：1999-10-19
申请人： Peter K. Naji
发明人： Peter K. Naji
IPC分类号： G06F1200
CPC分类号： G11C11/15 , G11C8/12 , G11C8/16
摘要： Processing equipment with embedded MRAMs, and a method of fabricating, including a data processing device fabricated on a semiconductor chip with MRAM cells fabricated on the chip to form one to all of the memories on the chip. Also included is a dual bank memory in communication with the data processing device and circuitry coupled to the data processing device and the dual bank memory for providing simultaneous read access to the dual bank memory.
摘要翻译：具有嵌入式MRAM的处理设备，以及一种制造方法，包括在半导体芯片上制造的数据处理设备，该芯片上制造有MRAM单元，以形成芯片上的所有存储器中的一个。还包括与数据处理设备和耦合到数据处理设备和双组存储器的电路通信的双行存储器，用于提供对双存储体存储器的同时读取访问。

20. 发明授权

US06515895B2 Non-volatile magnetic register 有权
公开(公告)号：US06515895B2
公开(公告)日：2003-02-04
申请号：US09774949
申请日：2001-01-31
申请人： Peter K. Naji
发明人： Peter K. Naji
IPC分类号： G11C1104
CPC分类号： G11C11/5607 , G11C14/0081 , G11C19/02
摘要： A non-volatile, bistable magnetic tunnel junction (MTJ) register cell includes first and second magnetic tunnel junctions connected for differential operation. The first MTJ is coupled between an easy axis line and an output terminal and the second MTJ is coupled between an inverse easy axis line and an inverse output terminal. A hard axis line is coupled magnetically to the MTJs and an enable line is coupled to the MTJs for enabling and disabling the differential operation. The MTJ register cell can be connected as a PIPO non-volatile register, a right or left non-volatile shift register, or a multi-bit bi-directional non-volatile shift register.

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