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11. 发明授权

US4937480A BICMOS buffer circuit 失效
标题翻译： BICMOS缓冲电路
公开(公告)号：US4937480A
公开(公告)日：1990-06-26
申请号：US373263
申请日：1989-06-27
申请人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma
发明人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma
IPC分类号： G11C7/12 , G11C8/06 , G11C8/10 , G11C11/418
CPC分类号： G11C8/10 , G11C11/418 , G11C7/12 , G11C8/06
摘要： A semiconductor integrated circuit includes an input buffer circuit, a decoder circuit and a plurality of memory cells. Each of the input buffer circuit and the decoder circuit consists of a combination of bipolar transistors and MOS transistors. In this combination various measures are taken to increase the operation speed and to reduce the electric power consumption. In an example thereof the data line load for the memory cells is constituted by Schottky barrier type diodes. In another example the load used for the respective emitter follower transistors is constituted by an MOS transistor operating as a variable resistance. In still another example, in a CMOS NOR ciruit of the decoder circuit the number of P channel MOS transistors are fewer than the number of N channel MOS transistors.

12. 发明授权

US4858191A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4858191A
公开(公告)日：1989-08-15
申请号：US131644
申请日：1987-12-11
申请人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma
发明人： Hisayuki Higuchi , Makoto Suzuki , Noriyuki Homma
IPC分类号： G11C7/12 , G11C8/06 , G11C8/10 , G11C11/418
CPC分类号： G11C8/10 , G11C11/418 , G11C7/12 , G11C8/06
摘要： A semiconductor integrated circuit includes an input buffer circuit, a decoder circuit and a plurality of memory cells. Each of the input buffer circuit and the decoder circuit consists of a combination of bipolar transistors and MOS transistors. In this combination various measures are taken to increase the operation speed and to reduce the electric power consumption. In an example thereof the data line load for the memory cells is constituted by Schottky barrier type diodes. In another example the load used for the respective emitter follower transistors is constituted by an MOS transistor operating as a variable resistance.In still another example, in a CMOS NOR circuit of the decoder circuit the number of P channel MOS transistors are fewer than the number of N channel MOS transistors.
摘要翻译：半导体集成电路包括输入缓冲电路，解码器电路和多个存储单元。输入缓冲电路和解码电路各自由双极晶体管和MOS晶体管组成。在这种组合中，采取各种措施来提高操作速度并降低电力消耗。在其示例中，存储单元的数据线负载由肖特基势垒型二极管构成。在另一示例中，用于各个射极跟随器晶体管的负载由作为可变电阻工作的MOS晶体管构成。在另一示例中，在解码器电路的CMOS NOR电路中，P沟道MOS晶体管的数量少于N沟道MOS晶体管的数量。

13. 发明授权

US4396460A Method of forming groove isolation in a semiconductor device 失效
标题翻译：在半导体器件中形成沟槽隔离的方法
公开(公告)号：US4396460A
公开(公告)日：1983-08-02
申请号：US380778
申请日：1982-05-21
申请人： Yoichi Tamaki , Tokuo Kure , Takeo Shiba , Hisayuki Higuchi
发明人： Yoichi Tamaki , Tokuo Kure , Takeo Shiba , Hisayuki Higuchi
IPC分类号： H01L21/76 , H01L21/306 , H01L21/3105 , H01L21/3213 , H01L21/763 , H01L21/308
CPC分类号： H01L21/31056 , H01L21/306 , H01L21/32134 , H01L21/763
摘要： After filling grooves with a filling material, this filling material is etched by the use of a double-layer film which is made of substances different from each other.The side etching of the lower film of the double-layer film and the etching of the filling material are alternately performed in such a manner that each etching is carried out a plurality of number of times. Thus, the upper surface of the filling material contained in each groove can be flattened.
摘要翻译：在用填充材料填充槽之后，通过使用由彼此不同的物质制成的双层膜来蚀刻该填充材料。双层膜的下膜的侧蚀刻和填充材料的蚀刻交替地以每次蚀刻多次进行的方式进行。因此，容纳在每个槽中的填充材料的上表面可以变平。

14. 发明授权

US06091629A High speed semiconductor memory apparatus including circuitry to increase writing and reading speed 失效
标题翻译：高速半导体存储装置包括增加写入和读取速度的电路
公开(公告)号：US06091629A
公开(公告)日：2000-07-18
申请号：US906883
申请日：1997-08-06
申请人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
发明人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
IPC分类号： G11C11/413 , G06F12/08 , G11C7/06 , G11C7/18 , G11C11/401 , G11C11/41 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： G11C7/18 , G06F12/0802 , G11C7/065
摘要： A semiconductor memory apparatus with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.
摘要翻译：一种具有存储器阵列的半导体存储器件，连接到读出放大器的第一全局位线，连接到写入放大器的第二全局位线，以及用于选择性地将多个位线连接到第一全局位线的选择电路，以及第二个全局位线。

15. 发明授权

US5253197A Semiconductor associative memory device with current sensing 失效
标题翻译：具有电流检测的半导体联想存储器件
公开(公告)号：US5253197A
公开(公告)日：1993-10-12
申请号：US580464
申请日：1990-09-11
申请人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi , Katsuhiro Shimohigashi , Takehisa Hayashi , Makoto Hanawa , Tadahiko Nishimukai
发明人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi , Katsuhiro Shimohigashi , Takehisa Hayashi , Makoto Hanawa , Tadahiko Nishimukai
IPC分类号： G06F12/08 , G06F12/10 , G11C15/04
CPC分类号： G11C15/04 , G06F12/0895 , G06F12/1054 , Y02B60/1225
摘要： In a first embodiment of a CAM (Content Addressable Memory) or cache memory of the present invention disclosed herein, comparing information stored in a memory cell with comparison input information is accomplished in a comparison circuit without first converting a readout current from the memory cell into voltage information. In another embodiment, a matching detection between first stored information outputted from a first memory cell array and second stored information outputted from a second memory cell array is accomplished by an integrally formed sensing and matching detection circuit which is characterized as having both sensing and matching detection capabilities. That is, the sensing and matching detection circuit senses both stored information and thereafter detects matching based on a sensing result.
摘要翻译：在本文公开的本发明的CAM（内容可寻址存储器）或高速缓冲存储器的第一实施例中，将存储在存储单元中的比较信息与比较输入信息进行比较，在比较电路中完成，而无需将来自存储单元的读出电流转换成电压信息。在另一个实施例中，从第一存储单元阵列输出的第一存储信息与从第二存储单元阵列输出的第二存储信息之间的匹配检测由一体形成的感测和匹配检测电路来实现，其特征在于具有检测和匹配检测能力也就是说，感测和匹配检测电路感测存储的信息，并且此后基于感测结果检测匹配。

16. 发明授权

US5107141A BiCMOS logic circuit using 0.5 micron technology and having an operating potential difference of less than 4 volts 失效
标题翻译： BiCMOS逻辑电路采用0.5微米技术，工作电位差小于4伏特
公开(公告)号：US5107141A
公开(公告)日：1992-04-21
申请号：US604454
申请日：1990-10-29
申请人： Kazuo Yano , Mitsuru Hiraki , Hisayuki Higuchi , Suguru Tachibana , Makoto Suzuki , Katsuhiro Shimohigashi
发明人： Kazuo Yano , Mitsuru Hiraki , Hisayuki Higuchi , Suguru Tachibana , Makoto Suzuki , Katsuhiro Shimohigashi
IPC分类号： H03K19/00 , H03K19/013 , H03K19/0944
CPC分类号： H03K19/0013 , H03K19/0136 , H03K19/09448
摘要： An output circuit portion of a BiCMOS logic circuit adapted to operating on a low voltage has an npn transistor Q5 connected between the power source Vcc and an output N6, and has an npn transistor Q6 connected between the output N6 and ground potential GND. The base of the npn transistor Q5 is driven by the drain output of p-channel MOSFETs MP3, MP4, and the base of the npn transistor Q6 is driven by the drain output of p-channel MOSFET QP5. When the power source voltage Vcc drops, the voltage applied between the drain and the source of MOSFET MP5 becomes small by the effect of V.sub.BE of the transistor Q6, but the drain current of the MOSFET MP5 changes little. Therefore, the BiCMOS circuit operates at high speeds (see FIG. 1) even when the power source voltage drops.
摘要翻译：适用于低电压工作的BiCMOS逻辑电路的输出电路部分具有连接在电源Vcc和输出N6之间的npn晶体管Q5，并具有连接在输出N6和地电位GND之间的npn晶体管Q6。 npn晶体管Q5的基极由p沟道MOSFET MP3，MP4的漏极输出驱动，npn晶体管Q6的基极由p沟道MOSFET QP5的漏极输出驱动。当电源电压Vcc下降时，通过晶体管Q6的VBE的影响，施加在MOSFET MP5的漏极和源极之间的电压变小，但MOSFET MP5的漏极电流变化较小。因此，即使当电源电压下降时，BiCMOS电路也以高速工作（参见图1）。

17. 发明授权

US4984058A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4984058A
公开(公告)日：1991-01-08
申请号：US225357
申请日：1988-07-28
申请人： Shuuichi Miyaoka , Nobuo Tamba , Toshikazu Arai , Hiroshi Higuchi , Hisayuki Higuchi
发明人： Shuuichi Miyaoka , Nobuo Tamba , Toshikazu Arai , Hiroshi Higuchi , Hisayuki Higuchi
IPC分类号： H01L27/11 , G11C11/401 , H01L21/3205 , H01L21/8244 , H01L23/52 , H01L23/528 , H01L27/02
CPC分类号： H01L27/0214 , H01L23/5286 , H01L24/06 , H01L2924/10253 , H01L2924/14 , H01L2924/3011 , Y10S257/915
摘要： In a semiconductor integrated circuit device having memory cell arrays, power source wirings are provided on the memory cell array in parallel with the long side of the memory cell array, thereby strengthening the power source wirings without increasing a chip size and planning reduction in power source impedances.
摘要翻译：在具有存储单元阵列的半导体集成电路器件中，与存储单元阵列的长边平行地在存储单元阵列上提供电源布线，从而在不增加芯片尺寸和规划电源减少的情况下加强电源布线阻力。

18. 发明授权

US4635090A Tapered groove IC isolation 失效
标题翻译：锥形沟槽IC隔离
公开(公告)号：US4635090A
公开(公告)日：1987-01-06
申请号：US733406
申请日：1985-05-13
申请人： Yoichi Tamaki , Tokuo Kure , Akira Sato , Hisayuki Higuchi
发明人： Yoichi Tamaki , Tokuo Kure , Akira Sato , Hisayuki Higuchi
IPC分类号： H01L21/762 , H01L27/04 , H01L21/302
CPC分类号： H01L21/76229 , H01L21/76232 , Y10S148/051 , Y10S148/085 , Y10S148/161 , Y10S148/168
摘要： A semiconductor device and the method of manufacturing the same are disclosed, the semiconductor device having a plurality of elements isolated by a groove having a gentle slope at the upper side wall, and a steep slope at the lower side wall. This groove provides low steps on its mouth and occupies a small area on the substrate, thus enabling an extremely high-density integrated circuit to be formed.
摘要翻译：公开了一种半导体器件及其制造方法，所述半导体器件具有通过在上侧壁具有缓和斜面的凹槽隔离的多个元件和在下侧壁处的陡峭斜坡。该槽在其口上提供低台阶并占据基板上的小面积，从而能够形成极高密度的集成电路。

19. 发明授权

US06839268B2 Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system 有权
标题翻译：半导体存储装置，半导体装置，数据处理装置及计算机系统
公开(公告)号：US06839268B2
公开(公告)日：2005-01-04
申请号：US10686569
申请日：2003-10-17
申请人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
发明人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
IPC分类号： G11C11/413 , G06F12/08 , G11C7/06 , G11C7/18 , G11C11/401 , G11C11/41 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： G11C7/18 , G06F12/0802 , G11C7/065
摘要： A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

20. 发明授权

US06515894B2 Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system 失效
公开(公告)号：US06515894B2
公开(公告)日：2003-02-04
申请号：US09988197
申请日：2001-11-19
申请人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
发明人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
IPC分类号： G11C1100
CPC分类号： G11C7/18 , G06F12/0802 , G11C7/065
摘要： A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

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