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11. 发明授权

US4792547A Pyrazine-2-carboxamide derivatives useful in treating allergic disease 失效
标题翻译：吡嗪-2-甲酰胺衍生物，用于治疗过敏性疾病
公开(公告)号：US4792547A
公开(公告)日：1988-12-20
申请号：US941918
申请日：1986-12-15
申请人： Yasuo Itoh , Hideo Kato , Eiichi Koshinaka , Nobuo Ogawa , Kazuya Mitani
发明人： Yasuo Itoh , Hideo Kato , Eiichi Koshinaka , Nobuo Ogawa , Kazuya Mitani
IPC分类号： C07D401/14 , C07D403/12 , C07D403/14 , A61K31/55 , A61K31/495
CPC分类号： C07D401/14 , C07D403/12 , C07D403/14
摘要： Novel pyrazine derivatives useful for treatment of bronchial asthma, allergic gastorenteric trouble, hay fever urticaria, allertic rhinitis, and allergic conjunctivitis, and pharmaceutical compositions thereof, are disclosed. The compounds have the formula I as follows: ##STR1## wherein R represents hydrogen or ##STR2## wherein R.sub.1 and R.sub.2 may be the same or different and each independently represents hydrogen, straight or branched-chain lower-alkyl, or cycloalkyl having three to six carbon atoms inclusive, phenyl which may be substituted with halogen, lower-alkyl, or lower-alkoxy, or wherein R.sub.1 and R.sub.2 together represent alkylene of four to six carbon atoms, inclusive, optionally interrupted by one or two nitrogen atoms or one oxygen atom and said ring being optionally substituted by straight or branched-chain lower-alkyl having one to six carbon atoms inclusive, hydroxy, or phenyl,and pharmaceutically-acceptable salts thereof.
摘要翻译：用于治疗支气管哮喘，过敏性胃炎，花粉荨麻疹，过敏性鼻炎和过敏性结膜炎的新颖吡嗪衍生物及其药物组合物。化合物具有如下式I：其中R表示氢或者其中R 1和R 2可以相同或不同，并且各自独立地表示氢，直链或支链低级烷基或具有三个至 6个碳原子，可被卤素，低级烷基或低级烷氧基取代的苯基，或其中R 1和R 2一起代表四至六个碳原子的亚烷基，包括任选地被一个或两个氮原子或一个氧所述环任选被具有1-6个碳原子的直链或支链低级烷基，羟基或苯基取代，及其药学上可接受的盐。

12. 发明授权

US4528287A 6-Fluoro-1, 4-dihydro-4-oxo-7-substituted piperazinylquinoline-3-carboxylic acids and the method for preparing the same 失效
标题翻译： 6-氟-1,4-二氢-4-氧代-7-取代的哌嗪基喹啉-3-羧酸及其制备方法
公开(公告)号：US4528287A
公开(公告)日：1985-07-09
申请号：US651423
申请日：1984-09-17
申请人： Yasuo Itoh , Hideo Kato , Nobuo Ogawa , Eiichi Koshinaka , Tomio Suzuki , Noriyuki Yagi
发明人： Yasuo Itoh , Hideo Kato , Nobuo Ogawa , Eiichi Koshinaka , Tomio Suzuki , Noriyuki Yagi
IPC分类号： C07D401/02 , C07D215/56 , A61K31/47 , C07D401/04
CPC分类号： C07D215/56
摘要： The invention is concerned with the novel piperazinylquinoline-3-carboxylic acids represented by formula (I) ##STR1## or a pharmacologically-acceptable salt thereof, a process for the preparation of them, and a pharmaceutical composition which contains these new compounds as active ingredient and can be used as the therapeutic agent against bacteria.
摘要翻译：本发明涉及由式（I）表示的新型哌嗪基喹啉-3-羧酸或其药学上可接受的盐，其制备方法和含有这些新化合物的药物组合物作为活性成分，可以用作抗细菌的治疗剂。

13. 再颁专利

USRE35838E Electrically erasable programmable read-only memory with NAND cell structure 失效
标题翻译：具有NAND单元结构的电可擦除可编程只读存储器
公开(公告)号：USRE35838E
公开(公告)日：1998-07-07
申请号：US430271
申请日：1995-04-28
申请人： Masaki Momodomi , Fujio Masuoka , Riichiro Shirota , Yasuo Itoh , Kazunori Ohuchi , Ryouhei Kirisawa
发明人： Masaki Momodomi , Fujio Masuoka , Riichiro Shirota , Yasuo Itoh , Kazunori Ohuchi , Ryouhei Kirisawa
IPC分类号： G11C16/16 , G11C17/00
CPC分类号： G11C16/16
摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected NAND cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.
摘要翻译：公开了具有NAND单元结构的可擦除可编程只读存储器，其具有设置在N型衬底上的存储单元。存储器单元被分成NAND单元块，每个单元块具有存储单元晶体管的串联阵列。每个晶体管具有浮置栅极，连接到字线的控制栅极和用作其源极和漏极的N型扩散层。这些半导体层形成在形成于基板的表面区域的P型阱层中。阱层用作表面击穿防止层。在数据擦除模式期间，存储在所有存储单元中的数据同时被擦除。在擦除模式之后的数据写入模式期间，当选择某个NAND单元块时，NAND单元块中的存储单元依次进行数据写入。当数据被写入所选择的NAND单元块中的某个存储单元中时，该特定存储单元的控制栅极被提供有如此高的电压，以形成强电场，以允许在浮置栅极的存储单元和阱层。因此，只能选择所选单元格。

14. 发明授权

US5546351A Non-volatile semiconductor memory device and memory system using the same 失效
公开(公告)号：US5546351A
公开(公告)日：1996-08-13
申请号：US326281
申请日：1994-10-20
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

15. 发明授权

US5452249A Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells 失效
标题翻译：具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件
公开(公告)号：US5452249A
公开(公告)日：1995-09-19
申请号：US210434
申请日：1994-03-21
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor changes the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译：非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。位线通过开关元件连接到触发器电路，并且晶体管改变位线。连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位，在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点中的一个连接到预定电位，从而将触发电路设置为第二状态在验证模式之前的状态。

16. 发明授权

US5400279A Nonvolatile semiconductor memory device with NAND cell structure 失效
标题翻译：具有NAND单元结构的非易失性半导体存储器件
公开(公告)号：US5400279A
公开(公告)日：1995-03-21
申请号：US67005
申请日：1993-05-26
申请人： Masaki Momodomi , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba
发明人： Masaki Momodomi , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/32 , G11C7/00
CPC分类号： G11C16/32 , G11C16/08 , G11C16/24 , G11C16/26
摘要： An electrically erasable programmable read-only memory has an array of programmable memory cells connected to parallel bit lines on a semiconductive substrate. The memory cells include NAND cell blocks each of which has a first selection transistor coupled to a corresponding bit line, a second selection transistor coupled to the ground potential, and a series array of memory cell transistors each having a floating gate and a control gate. Word lines are respectively connected to the control gates of the memory cell transistors. In a data read mode, a selection transistor of a certain NAND cell block including a selected memory cell transistor is rendered conductive to connect this cell block to a bit line associated therewith. Under such a condition, a low or "L" level voltage is applied by a row decoder & bootstrap circuit section to a word line connected to the selected memory cell transistor, and a pulse voltage signal having a high or "H" level is supplied by the row decoder & bootstrap circuit section to the remaining word lines, so that data stored in the selected memory cell is read out. The "H" level of the voltage signal is higher than the power supply voltage and yet lower than a normal "H" level used in data write and erase modes. The pulse width of the pulse voltage signal is shorter than the period of one read cycle.
摘要翻译：电可擦除可编程只读存储器具有连接到半导体衬底上的并行位线的可编程存储器单元阵列。存储器单元包括NAND单元块，每个NAND单元块具有耦合到对应位线的第一选择晶体管，耦合到地电位的第二选择晶体管，以及每个具有浮置栅极和控制栅极的存储单元晶体管的串联阵列。字线分别连接到存储单元晶体管的控制栅极。在数据读取模式中，将包括所选存储单元晶体管的某个NAND单元块的选择晶体管导通，以将该单元块连接到与其相关联的位线。在这种情况下，由行解码器和自举电路部分将低电平或“L”电平施加到连接到所选择的存储单元晶体管的字线，并且提供具有高或“H”电平的脉冲电压信号通过行解码器和引导电路部分到剩余的字线，使得读出存储在所选存储单元中的数据。电压信号的“H”电平高于电源电压，但低于在数据写入和擦除模式下使用的正常“H”电平。脉冲电压信号的脉冲宽度比一个读周期的周期短。

17. 发明授权

US5361227A Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US5361227A
公开(公告)日：1994-11-01
申请号：US992653
申请日：1992-12-18
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

18. 发明授权

US5278794A NAND-cell type electrically erasable and programmable read-only memory with redundancy circuit 失效
标题翻译：具有冗余电路的NAND单元型电可擦除可编程只读存储器
公开(公告)号：US5278794A
公开(公告)日：1994-01-11
申请号：US960882
申请日：1992-10-14
申请人： Yoshiyuki Tanaka , Yasuo Itoh , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka
发明人： Yoshiyuki Tanaka , Yasuo Itoh , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C29/00 , G11C29/04 , G11C11/40 , G11C5/02
CPC分类号： G11C29/789 , G11C16/0483 , G11C29/808 , G11C29/82
摘要： A NAND-cell type electrically erasable and programmable read only memory includes an array of rows and columns of memory cells associated with parallel bit lines on a semiconductive substrate. Each memory cell essentially consists of a floating-gate field effect transistor having a floating gate and an insulated control gate. The memory cell array is divided into a plurality of cell blocks, each of which includes NAND cell sections each including a predetermined number of a series-connected memory cell transistors. A redundancy cell section is provided which includes an array of redundancy memory cells containing at least one spare cell block. A row redundancy circuit is connected to a row decoder, and is responsive to an address buffer. The redundancy circuit replaces a defective block containing a defective memory cell or cells with the spare cell block.
摘要翻译： NAND单元型电可擦除和可编程只读存储器包括与半导体基板上的并行位线相关联的存储单元的行和列阵列。每个存储单元基本上由具有浮置栅极和绝缘控制栅极的浮栅场效应晶体管组成。存储单元阵列被分成多个单元块，每个单元块包括每个包括预定数量的串联存储单元晶体管的NAND单元部分。提供冗余单元部分，其包括包含至少一个备用单元块的冗余存储单元的阵列。行冗余电路连接到行解码器，并响应于地址缓冲器。冗余电路用备用单元块替代含有缺陷存储单元或单元的缺陷块。

19. 发明授权

US5050125A Electrically erasable programmable read-only memory with NAND cellstructure 失效
标题翻译：具有NAND单元结构的电可擦除可编程只读存储器
公开(公告)号：US5050125A
公开(公告)日：1991-09-17
申请号：US272404
申请日：1988-11-17
申请人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
发明人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
IPC分类号： G11C16/04 , G11C16/08 , G11C16/30 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/08 , G11C16/30
摘要： An erasable programmable read-only memory with a NAND cell structure including NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected is series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" Level voltage (approximately O V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.
摘要翻译：具有包括NAND单元块的NAND单元结构的可擦除可编程只读存储器，每个NAND单元块具有连接到相应位线的选择晶体管和连接的存储单元晶体管。字线连接到单元晶体管的控制栅极。在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。提供控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约为0V），对位于所选择的单元之间的字线或字线施加“H”电平电压（大约20V）字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入特定位线的数据相对应的电压，以及将“H”和“L”电平电压之间的中间电压施加到未选择的位线，从而通过隧道将数据写入所选择的单元。如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

20. 发明授权

US5043942A Nand cell type programmable read-only memory with common control gate driver circuit 失效
标题翻译： N型单元型可编程只读存储器，具有公共控制栅极驱动电路
公开(公告)号：US5043942A
公开(公告)日：1991-08-27
申请号：US532627
申请日：1990-06-04
申请人： Yoshihisa Iwata , Masaki Momodomi , Yasuo Itoh , Tomoharu Tanaka , Hideko Odaira
发明人： Yoshihisa Iwata , Masaki Momodomi , Yasuo Itoh , Tomoharu Tanaka , Hideko Odaira
IPC分类号： G11C17/00 , G11C8/10 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/16 , H01L27/112
摘要： A NAND cell type EEPROM has a substrate, parallel bit lines formed above the substrate, and a memory cell section including an array of NAND type cell units associated with the same corresponding bit line. Each of the NAND type cell units has a series-circuit of eight data storage transistors and at least one selection transistor. Each data storage transistor has a floating gate for storing carriers injected thereinto by tunneling and a control gate respectively connected to word lines. A control gate driver circuit is provided in common for all the NAND type cell units that are assisted with the same bit line. Transfer gates are connected between the common driver circuit and the NAND cell units.
摘要翻译： NAND单元型EEPROM具有基板，形成在基板上方的并行位线以及包括与相同对应位线相关联的NAND型单元单元的阵列的存储单元部分。每个NAND型单元单元具有八个数据存储晶体管和至少一个选择晶体管的串联电路。每个数据存储晶体管具有用于存储通过隧道注入的载流子的浮动栅极和分别连接到字线的控制栅极。为同一位线辅助的所有NAND型单元单元共同提供控制栅极驱动电路。传输门连接在公共驱动电路和NAND单元之间。

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