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11. 发明授权

US07089514B2 Defect diagnosis for semiconductor integrated circuits 失效
标题翻译：半导体集成电路缺陷诊断
公开(公告)号：US07089514B2
公开(公告)日：2006-08-08
申请号：US10710879
申请日：2004-08-10
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Francis Gravel , Leendert M. Huisman , Phillip J. Nigh , Leah M. P. Pastel , Kenneth Rowe , Thomas G. Sopchak , David E. Sweenor
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Francis Gravel , Leendert M. Huisman , Phillip J. Nigh , Leah M. P. Pastel , Kenneth Rowe , Thomas G. Sopchak , David E. Sweenor
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/318342
摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.
摘要翻译：一种半导体芯片缺陷诊断方法。该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

12. 发明授权

US08451018B2 Bit failure signature identification 有权
标题翻译：位故障签名识别
公开(公告)号：US08451018B2
公开(公告)日：2013-05-28
申请号：US12706228
申请日：2010-02-16
申请人： Thomas D. Furland , Robert J. Milne, Jr. , Leah M. P. Pastel , Kevin W. Stanley , Robert C. Virun
发明人： Thomas D. Furland , Robert J. Milne, Jr. , Leah M. P. Pastel , Kevin W. Stanley , Robert C. Virun
IPC分类号： G01R31/26
CPC分类号： G01R31/31703 , G01R31/31935
摘要： A method, system, and program product for identifying at least one bit failure among a plurality of semiconductor chips are provided. A first aspect of the invention provides a method of identifying at least one bit failure signature among a plurality of semiconductor chips, the method comprising: counting failures of each failing bit among the plurality of semiconductor chips; determining a most commonly failing bit (MCFB) among the failing bits; establishing a bit failure signature including the MCFB; counting failures of each failing bit on semiconductor chips on which the MCFB fails; determining a next most commonly failing bit (NMCFB) among the failing bits on semiconductor chips on which the MCFB fails; determining whether the NMCFB tends to fail when the MCFB fails; and in response to a determination that the NMCFB tends to fail when the MCFB fails, adding the NMCFB to the bit failure signature.
摘要翻译：提供了用于识别多个半导体芯片中的至少一个位故障的方法，系统和程序产品。本发明的第一方面提供了一种识别多个半导体芯片中的至少一个位故障签名的方法，所述方法包括：对所述多个半导体芯片中的每个故障位进行计数故障; 确定故障位中最常见的故障位（MCFB）; 建立包括MCFB在内的位故障签名; 在MCFB故障的半导体芯片上的每个故障位的计数失败; 确定在MCFB故障的半导体芯片上的故障位中的下一个最常故障位（NMCFB）; 确定当MCFB发生故障时，NMCFB是否会失败; 并且响应于当MCFB失败时NMCFB趋向于失败的确定，将NMCFB添加到位故障签名。

13. 发明授权

US06880136B2 Method to detect systematic defects in VLSI manufacturing 失效
标题翻译：检测VLSI制造系统缺陷的方法
公开(公告)号：US06880136B2
公开(公告)日：2005-04-12
申请号：US10191212
申请日：2002-07-09
申请人： Leendert M. Huisman , Maroun Kassab , Leah M. P. Pastel
发明人： Leendert M. Huisman , Maroun Kassab , Leah M. P. Pastel
IPC分类号： H01L21/66 , G06F17/50 , G01R31/26 , H01L21/00
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Defects in manufacturing of IC devices are analyzed by testing the devices for defects using results of LSSD technology to find at least one failing pattern that contains incorrect values. The failing latches are used as a starting point to trace back through combinational logic feeding the failing latches, until controllable latches are encountered. A decision is then made to continue the back tracing or not depending on whether the latter latches were clocked during the application of one of the failing patterns or not.
摘要翻译：通过使用LSSD技术的结果测试设备的缺陷来分析IC器件制造中的缺陷，以找到至少一个包含不正确值的故障模式。使用故障锁存器作为起始点，通过组合逻辑来跟踪故障锁存器，直到遇到可控制的锁存器。然后，决定是否在应用其中一种失败模式的情况下是否继续后跟踪。

14. 发明授权

US06675323B2 Incremental fault dictionary 有权
标题翻译：增量故障字典
公开(公告)号：US06675323B2
公开(公告)日：2004-01-06
申请号：US09682456
申请日：2001-09-05
申请人： Thomas W. Bartenstein , Douglas C. Heaberlin , Leendert M. Huisman , Thomas F. Mechler , Leah M. P. Pastel , Glen E. Richard , Raymond J. Rosner
发明人： Thomas W. Bartenstein , Douglas C. Heaberlin , Leendert M. Huisman , Thomas F. Mechler , Leah M. P. Pastel , Glen E. Richard , Raymond J. Rosner
IPC分类号： G06F1100
CPC分类号： G06F11/2252
摘要： An incremental fault dictionary in which the diagnostic simulation results of current tests are stored for future use. Diagnostic simulation results are incrementally added to the fault dictionary, and information in the incremental fault dictionary is used to avoid expensive redundant fault simulations. The size of the incremental fault dictionary is maintained within user definable bounds by identifying and deleting faults that need not be maintained in the incremental fault dictionary. The incremental fault dictionary beneficially provides more accurate and faster diagnostics than a typical prior art diagnostic fault simulation.
摘要翻译：增量故障字典，其中存储当前测试的诊断模拟结果以供将来使用。诊断仿真结果逐渐添加到故障字典中，增量故障字典中的信息用于避免昂贵的冗余故障模拟。通过识别和删除不需要在增量故障字典中维护的故障，增量故障字典的大小保持在用户可定义的界限内。增量故障字典有益地提供比典型的现有技术诊断故障模拟更准确和更快的诊断。

15. 发明授权

US08347260B2 Method of designing an integrated circuit based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage 有权
标题翻译：基于可制造性，测试覆盖和可选地诊断覆盖的组合来设计集成电路的方法
公开(公告)号：US08347260B2
公开(公告)日：2013-01-01
申请号：US12880228
申请日：2010-09-13
申请人： Kerry Bernstein , James A. Culp , Leah M. P. Pastel , Kirk D. Peterson , Norman J. Rohrer
发明人： Kerry Bernstein , James A. Culp , Leah M. P. Pastel , Kirk D. Peterson , Norman J. Rohrer
IPC分类号： G06F11/22
CPC分类号： G06F17/5045 , G06F2217/12 , Y02P90/265
摘要： Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.
摘要翻译：披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。或者，可以根据DFM修改建立集成电路的测试覆盖。或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。

16. 发明授权

US07064570B2 Method for locating IDDQ defects using multiple controlled collapse chip connections current measurement on an automatic tester 失效
标题翻译：使用多个受控崩溃芯片连接在自动测试仪上进行电流测量来定位IDDQ缺陷的方法
公开(公告)号：US07064570B2
公开(公告)日：2006-06-20
申请号：US10665321
申请日：2003-09-20
申请人： Patrick H. Buffet , Douglas C. Heaberlin , Leah M. P. Pastel , Yu H. Sun
发明人： Patrick H. Buffet , Douglas C. Heaberlin , Leah M. P. Pastel , Yu H. Sun
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2843 , G01R31/2853 , G01R31/3008 , G01R31/3012
摘要： A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.
摘要翻译：公开了一种用于改善I DDQ 缺陷测试中的信噪比的方法。集成电路被分成多个区域，并且每个区域由终端设置和限制。在集成电路内激活了一个DDQ 缺陷以产生缺陷电流。在提供给它的端子处测量在每个区域内产生的缺陷电流的量。基于每个区域上的I＆lt; DDQ＆lt; DDQ＆lt;＆gt;当前测量结果，创建I＆lt; DDQ＆gt;当前地图。通过分析当前地图，确定缺陷的存在和位置。基于确定，分离了I DDQ 缺陷。

17. 发明授权

US06677774B2 Method for locating IDDQ defects using multiple controlled collapse chip connections current measurement on an automatic tester 失效
标题翻译：使用多个受控崩溃芯片连接在自动测试仪上进行电流测量来定位IDDQ缺陷的方法
公开(公告)号：US06677774B2
公开(公告)日：2004-01-13
申请号：US09681917
申请日：2001-06-26
申请人： Patrick H. Buffet , Douglas C. Heaberlin , Leah M. P. Pastel , Yu H. Sun
发明人： Patrick H. Buffet , Douglas C. Heaberlin , Leah M. P. Pastel , Yu H. Sun
IPC分类号： G01R3126
CPC分类号： G01R31/2843 , G01R31/2853 , G01R31/3008 , G01R31/3012
摘要： A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.
摘要翻译：公开了一种用于提高IDDQ缺陷测试中的信噪比的方法。集成电路被分成多个区域，并且每个区域由终端设置和限制。激活IDDQ缺陷以在集成电路内产生IDDQ缺陷电流。在提供给它的端子处测量在每个区域内产生的IDDQ缺陷电流量。根据每个区域的IDDQ电流测量，创建一个IDDQ当前图。通过分析IDDQ当前图，确定缺陷的存在和位置。根据确定，IDDQ缺陷是孤立的。

18. 发明申请

US20080284459A1 Testing Using Independently Controllable Voltage Islands 审中-公开
标题翻译：使用独立可控电压岛进行测试
公开(公告)号：US20080284459A1
公开(公告)日：2008-11-20
申请号：US12185151
申请日：2008-08-04
申请人： Anne E. Gattiker , Phil Nigh , Leah M. P. Pastel , Steven F. Oakland , Jody VanHorn , Paul S. Zuchowski
发明人： Anne E. Gattiker , Phil Nigh , Leah M. P. Pastel , Steven F. Oakland , Jody VanHorn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318575 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands, each powered by a respective island source voltage, and a testing circuit, coupled to the voltage islands, and powered by a global source voltage that is always on during test, wherein each island source voltage may be independently controlled during test.
摘要翻译：一种电压岛结构，其中每个电压岛的源电压可以在基于扫描的测试期间独立地接通/关断或调节。该架构包括多个电压岛，每个电压岛由相应的岛源电压供电，以及耦合到电压岛的测试电路，并由在测试期间始终导通的全局源电压供电，其中每个岛源电压可以是在测试期间独立控制。

19. 发明授权

US07428675B2 Testing using independently controllable voltage islands 失效
标题翻译：使用独立可控电压岛测试
公开(公告)号：US07428675B2
公开(公告)日：2008-09-23
申请号：US10545961
申请日：2003-02-20
申请人： Anne E. Gattiker , Phil Nigh , Leah M. P. Pastel , Steven F. Oakland , Jody VanHorn , Paul S. Zuchowski
发明人： Anne E. Gattiker , Phil Nigh , Leah M. P. Pastel , Steven F. Oakland , Jody VanHorn , Paul S. Zuchowski
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318575 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands (102, 104), each powered by a respective island source voltage (VDDI1, VDDI2), and a testing circuit (116), coupled to the voltage islands, and powered by a global source voltage (Vg) that is always on during test, wherein each island source voltage may be independently controlled (106, 108) during test.
摘要翻译：一种电压岛结构，其中每个电压岛的源电压可以在基于扫描的测试期间独立地接通/关断或调节。该架构包括多个电压岛（102,104），每个电压岛由相应的岛源电压（VDDI 1，VDDI 2）供电，以及耦合到电压岛的测试电路（116），并由全局源在测试期间总是导通的电压（Vg），其中每个岛源电压可以在测试期间被独立地控制（106,108）。

20. 发明申请

US20080129324A1 Hot Switchable Voltage Bus for Iddq Current Measurements 审中-公开
标题翻译：可开关电压总线，用于Iddq电流测量
公开(公告)号：US20080129324A1
公开(公告)日：2008-06-05
申请号：US10595526
申请日：2003-11-05
申请人： Leah M. P. Pastel
发明人： Leah M. P. Pastel
IPC分类号： G01R31/30
CPC分类号： G01R31/3008
摘要： A voltage island system including a hot-switchable voltage bus for IDDQ current measurements. The voltage island system includes a plurality of voltage islands (V1, V2, . . . , Vn), a global power system, and a quiescent power system. The global power system includes a plurality of on-chip global header devices (H1, H2, . . . , Hn) for selectively providing a voltage VDDg to the plurality of voltage islands in response to global header control signals (x1, x2, . . . , xn), respectively. A global VDDg power supply provides power to the global header devices (H1, H2, . . . , Hn) via a VDDg power distribution grid/bus. The quiescent power system includes a plurality of on-chip quiescent header devices (H1q, H2q, . . . , Hnq) for selectively providing a quiescent voltage VDDq to the plurality of voltage islands in response to quiescent header control signals x1q, x2q, . . . , xnq, respectively. A quiescent VDDq power supply provides power to the quiescent header devices via a VDDq power distribution grid/bus.
摘要翻译：一个电压岛系统，包括用于IDDQ电流测量的热切换电压总线。电压岛系统包括多个电压岛（V 1，V 2，...，Vn），全球电力系统和静态电力系统。全球电力系统包括多个片上全局头部装置（H 1，H 2，...，Hn），用于响应于全局头部控制信号（x 1，...，H n）选择性地向多个电压岛提供电压VDDg， x 2，...，xn）。全局VDDg电源通过VDDg配电网/总线为全局总线设备（H 1，H 2，...，Hn）提供电源。静态电力系统包括多个片上静态头部装置（H 1 q，H 2 q，...，Hnq），用于响应于静态头部控制信号x而选择性地向多个电压岛提供静态电压VDDq 1 q，x 2 q，。。。，xnq。静态VDDq电源通过VDDq配电网/总线为静态接头设备供电。

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