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1. 发明授权

US06675323B2 Incremental fault dictionary 有权
标题翻译：增量故障字典
公开(公告)号：US06675323B2
公开(公告)日：2004-01-06
申请号：US09682456
申请日：2001-09-05
申请人： Thomas W. Bartenstein , Douglas C. Heaberlin , Leendert M. Huisman , Thomas F. Mechler , Leah M. P. Pastel , Glen E. Richard , Raymond J. Rosner
发明人： Thomas W. Bartenstein , Douglas C. Heaberlin , Leendert M. Huisman , Thomas F. Mechler , Leah M. P. Pastel , Glen E. Richard , Raymond J. Rosner
IPC分类号： G06F1100
CPC分类号： G06F11/2252
摘要： An incremental fault dictionary in which the diagnostic simulation results of current tests are stored for future use. Diagnostic simulation results are incrementally added to the fault dictionary, and information in the incremental fault dictionary is used to avoid expensive redundant fault simulations. The size of the incremental fault dictionary is maintained within user definable bounds by identifying and deleting faults that need not be maintained in the incremental fault dictionary. The incremental fault dictionary beneficially provides more accurate and faster diagnostics than a typical prior art diagnostic fault simulation.
摘要翻译：增量故障字典，其中存储当前测试的诊断模拟结果以供将来使用。诊断仿真结果逐渐添加到故障字典中，增量故障字典中的信息用于避免昂贵的冗余故障模拟。通过识别和删除不需要在增量故障字典中维护的故障，增量故障字典的大小保持在用户可定义的界限内。增量故障字典有益地提供比典型的现有技术诊断故障模拟更准确和更快的诊断。

2. 发明授权

US06901542B2 Internal cache for on chip test data storage 失效
标题翻译：用于片内测试数据存储的内部缓存
公开(公告)号：US06901542B2
公开(公告)日：2005-05-31
申请号：US09927011
申请日：2001-08-09
申请人： Thomas W. Bartenstein , L. Owen Farnsworth, III , Douglas C. Heaberlin , Edward E. Horton, III , Leendert M. Huisman , Leah M. Pastel , Glen E. Richard , Raymond J. Rosner , Francis Woytowich
发明人： Thomas W. Bartenstein , L. Owen Farnsworth, III , Douglas C. Heaberlin , Edward E. Horton, III , Leendert M. Huisman , Leah M. Pastel , Glen E. Richard , Raymond J. Rosner , Francis Woytowich
IPC分类号： G11C29/26 , G01R31/3193 , G01R31/3177 , G01R31/3187
CPC分类号： G11C29/26
摘要： A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an acceptable testing result; and storing data in the designated portion of the memory for retrieval at a later time. Provision for soft repair of the selected memory is made. Test data can be compressed before being stored in the designated memory.
摘要翻译：公开了一种测试具有存储器的半导体器件的方法。该方法包括选择存储器的一部分; 测试存储器的选定部分; 响应于可接受的测试结果，将存储器的所选部分指定为指定存储器; 并在稍后的时间将数据存储在存储器的指定部分中以进行检索。对所选择的存储器进行软修复。测试数据可以在存储在指定的存储器中之前进行压缩。

3. 发明授权

US06721914B2 Diagnosis of combinational logic circuit failures 有权
标题翻译：组合逻辑电路故障诊断
公开(公告)号：US06721914B2
公开(公告)日：2004-04-13
申请号：US09827425
申请日：2001-04-06
申请人： Thomas W. Bartenstein , Douglas C. Heaberlin , Leendert M. Huisman
发明人： Thomas W. Bartenstein , Douglas C. Heaberlin , Leendert M. Huisman
IPC分类号： G01R3128
CPC分类号： G01R31/317
摘要： A method for diagnosing defects in an integrated circuit comprising: providing a set of failing test patterns; for each failing test pattern in the set of test patterns determining if a single stuck-at fault could cause the failing test pattern and determining a node on which a defect causing the single stuck-at fault could reside; selecting those failing test patterns that could be caused by a single stuck-at fault; and for those selected failing test patterns determining a first set of sets of nodes, such that each of the selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from the first set of sets of nodes.
摘要翻译：一种用于诊断集成电路中的缺陷的方法，包括：提供一组故障测试图案; 对于测试模式集合中的每个故障测试模式，确定单个卡住故障是否可能导致故障测试模式，并确定导致单个卡住故障的故障可能存在的节点; 选择可能由单一故障引起的故障测试模式; 并且对于那些选择的故障测试模式来确定第一组节点，使得所选择的故障测试模式中的每一个可能由每个节点上的至少一个节点上的卡住零或卡住的一个导致从第一组节点。

4. 发明授权

US07496816B2 Isolating the location of defects in scan chains 有权
标题翻译：隔离扫描链中缺陷的位置
公开(公告)号：US07496816B2
公开(公告)日：2009-02-24
申请号：US11385534
申请日：2006-03-20
申请人： Thomas W. Bartenstein , Joseph Swenton , David Sliwinski
发明人： Thomas W. Bartenstein , Joseph Swenton , David Sliwinski
IPC分类号： G01R31/28
CPC分类号： G01R31/318566
摘要： A system and method for isolating defects in scan chains by performing diagnostics fault simulation on chosen faults that are consistent with the nature of a scan chain defect, while keeping information about predictable failures. The effects of defects at specific locations on the scan chain are modeled by compositing the effects of a subset of the faults for each defect. Each composite, which models a specific scan chain defect, is evaluated in terms of how well it predicts the failures measured at a tester, and assigned a score based on that evaluation. The composite with the highest score identifies the modeled defect which is the closest to predicting the results measured at the tester, and therefore the location on the scan chain that has the highest probability of containing the actual defect.
摘要翻译：通过对与扫描链缺陷的性质相一致的选定故障执行诊断故障模拟，同时保留有关可预测故障的信息，来分离扫描链中的缺陷的系统和方法。通过对每个缺陷的故障子集的影响进行合成来建模扫描链上特定位置处缺陷的影响。根据对预测在测试者测量的故障情况进行评估，并根据该评估指定了一个分数，对每个复合材料模拟特定的扫描链缺陷进行了评估。具有最高分数的复合体识别模拟缺陷，其最接近于预测在测试者处测量的结果，因此扫描链上具有包含实际缺陷概率最高的位置。

5. 发明授权

US08397113B2 Method and system for identifying power defects using test pattern switching activity 有权
标题翻译：使用测试模式切换活动识别功率缺陷的方法和系统
公开(公告)号：US08397113B2
公开(公告)日：2013-03-12
申请号：US12903044
申请日：2010-10-12
申请人： Thomas W. Bartenstein , Patrick Wayne Gallagher
发明人： Thomas W. Bartenstein , Patrick Wayne Gallagher
IPC分类号： G01R13/28 , G06F11/00
CPC分类号： G06F11/2273 , G01R31/30 , G01R31/318342
摘要： A method and system for identifying power defects using test pattern switching activity is disclosed. In one embodiment, a plurality of test patterns is applied to a circuit under test, and failure test patterns are identified from the plurality of test patterns by comparing the test result with the predicted test result. A switching activity count is obtained for each of the plurality of test patterns. Based on the switching activity count, ranks for each of the plurality of test patterns are provided. A correlation analysis is performed between the failure test patterns and the ranks of the switching activities. When there is a high correlation between the failure test pattern and the ranks of the switching activities, it is determined that the circuit likely contains a power defect. A power defect analysis is performed under the presence of the high correlation.
摘要翻译：公开了一种使用测试模式切换活动识别功率缺陷的方法和系统。在一个实施例中，将多个测试图案应用于被测电路，并通过将测试结果与预测的测试结果进行比较，从多个测试模式中识别出故障测试模式。为多个测试图案中的每一个获得切换活动计数。基于切换活动计数，提供多个测试图案中的每一个的等级。在故障测试模式和交换活动的级别之间进行相关分析。当故障测试模式与切换活动级别之间存在很高的相关性时，确定该电路可能包含电源缺陷。在高相关性的存在下进行功率缺陷分析。

6. 发明授权

US06708306B2 Method for diagnosing failures using invariant analysis 有权
标题翻译：使用不变性分析诊断故障的方法
公开(公告)号：US06708306B2
公开(公告)日：2004-03-16
申请号：US09739048
申请日：2000-12-18
申请人： Thomas W. Bartenstein , Joseph M. Swenton
发明人： Thomas W. Bartenstein , Joseph M. Swenton
IPC分类号： G01R3128
CPC分类号： G01R31/318342
摘要： A method for diagnosing failures within an integrated circuit where known diagnostic fault simulators are unable to detect failure mechanisms which do not conform to known failure models. Basic boolean equations are used to describe the internal nodes forming the logic. These equations are then evaluated by way of a good machine simulation to determine which of the equations are (most) true for failing test patterns and (most) false for passing patterns. At the end of the good machine simulation a score is calculated to determine the number of times (or percentage) for which the equation is true for failing patterns and false for passing patterns. The method is particularly effective for finding shorted nets pairs in which the failure mechanism does not fall within known models. The method described is instrumental in greatly reducing the time required for manual analysis of failure mechanisms not conforming to known models.
摘要翻译：用于诊断集成电路中的故障的方法，其中已知的诊断故障模拟器不能检测到不符合已知故障模型的故障机制。基本布尔方程用于描述形成逻辑的内部节点。然后通过良好的机器模拟来评估这些方程，以确定对于失败的测试模式，（大多数）假设通过模式中哪些方程是（大多数）为真。在良好的机器模拟结束时，计算分数以确定方程对于失败模式为真的次数（或百分比），对于通过模式为假。该方法对于找到其中故障机制不在已知模型内的短网对特别有效。所描述的方法有助于大大减少手动分析不符合已知模型的故障机制所需的时间。

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