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11. 发明授权

US5859797A Biasing circuit for UPROM cells with low voltage supply 失效
标题翻译：低压电源的UPROM单元的偏置电路
公开(公告)号：US5859797A
公开(公告)日：1999-01-12
申请号：US846753
申请日：1997-04-30
申请人： Marco Maccarrone , Jacopo Mulatti , Carla Maria Golla
发明人： Marco Maccarrone , Jacopo Mulatti , Carla Maria Golla
IPC分类号： G11C16/30 , G11C7/00
CPC分类号： G11C16/30
摘要： A circuit for generating biasing signals in reading of a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, as well as MOS transistors connecting the memory element with a reference low supply voltage comprises a voltage booster for generating a first voltage output signal to be applied to the control terminal of the memory element and a limitation network for the voltage signal connected to the output of the voltage booster. There is also provided a circuit portion for generating a second voltage output signal to be applied to the control terminal of one of the above mentioned transistors. This circuit portion comprises a timing section interlocked with the voltage booster of a section generating the second voltage signal.
摘要翻译：一种用于在读入包括EPROM或闪存类型的至少一个存储元件并具有要偏置的控制端子和导电端子的冗余UPROM单元的电路中产生偏置信号的电路，以及连接存储元件与参考电压的MOS晶体管低电源电压包括用于产生要施加到存储元件的控制端的第一电压输出信号的电压升压器和连接到升压器的输出的电压信号的限制网络。还提供了用于产生要施加到上述晶体管之一的控制端子的第二电压输出信号的电路部分。该电路部分包括与产生第二电压信号的部分的升压器互锁的定时部分。

12. 发明授权

US5805500A Circuit and method for generating a read reference signal for nonvolatile memory cells 失效
标题翻译：用于产生用于非易失性存储单元的读取参考信号的电路和方法
公开(公告)号：US5805500A
公开(公告)日：1998-09-08
申请号：US877921
申请日：1997-06-18
申请人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone
发明人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone
IPC分类号： G11C16/28 , G11C16/06
CPC分类号： G11C16/28
摘要： The current flowing through a cell to be read, forming part of a nonvolatile memory array and presenting a characteristic with a predetermined slope, is amplified N times and compared with a reference current presenting a two portion characteristic: a first portion extending between a predetermined threshold value and a trigger value, and presenting a slope equal to that of the memory cell characteristic, and a second portion extending from the trigger value, and presenting a slope amplified N times with respect to that of the cell characteristic and therefore equal to the amplified slope of the cell.
摘要翻译：流过待读取的单元的电流，形成非易失性存储器阵列的一部分并呈现具有预定斜率的特性，被放大N倍，并与呈现两部分特性的参考电流进行比较：在预定阈值之间延伸的第一部分值和触发值，并且呈现与存储器单元特性相同的斜率，以及从触发值延伸的第二部分，并且呈现相对于单元特性的N倍的斜率，因此等于放大的细胞斜率

13. 发明授权

US5546054A Current source having voltage stabilizing element 失效
标题翻译：电流源具有稳压元件
公开(公告)号：US5546054A
公开(公告)日：1996-08-13
申请号：US377524
申请日：1995-01-20
申请人： Marco Maccarrone , Marco Olivo , Carla M. Golla
发明人： Marco Maccarrone , Marco Olivo , Carla M. Golla
IPC分类号： G11C17/00 , G05F3/24 , G05F3/26 , H03F1/30 , H03B5/24 , G05F3/16 , H03K3/011 , H03K3/03
CPC分类号： G05F3/262
摘要： A current source including a current mirror circuit and an active load circuit which form a reference branch, for setting a reference current value, and a mirroring branch, defining an output current value, connected between supply and ground. A voltage stabilizing transistor is interposed between the current mirror circuit and the load circuit in the reference branch only, and is so biased as to maintain its gate terminal at a predetermined voltage. As such, the potential with respect to ground of the drain terminal of the reference branch load transistor is fixed, so that its drain-source voltage drop (and the current through it) is substantially independent of supply voltage. The current source may be used to advantage in an oscillator for generating the: clock signal of a nonvolatile memory.
摘要翻译：电流源包括形成用于设定参考电流值的参考支路的电流镜电路和有源负载电路以及连接在电源和地之间的限定输出电流值的镜像支路。稳压晶体管仅插入在电流镜电路和参考支路中的负载电路之间，并被偏置以将其栅极端子保持在预定电压。因此，参考分支负载晶体管的漏极端子的接地电位是固定的，使得其漏 - 源电压降（和通过它的电流）基本上不依赖于电源电压。在振荡器中可以使用电流源来产生非易失性存储器的：时钟信号。

14. 发明授权

US5532972A Method and circuit for timing the reading of nonvolatile memories 失效
标题翻译：用于定时读取非易失性存储器的方法和电路
公开(公告)号：US5532972A
公开(公告)日：1996-07-02
申请号：US391920
申请日：1995-02-21
申请人： Luigi Pascucci , Silvia Padoan , Carla M. Golla , Marco Maccarrone , Marco Olivo
发明人： Luigi Pascucci , Silvia Padoan , Carla M. Golla , Marco Maccarrone , Marco Olivo
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C7/22 , G11C16/02 , G11C16/32 , G11C7/00
CPC分类号： G11C7/02 , G11C16/32 , G11C7/1006 , G11C7/22
摘要： A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noise suppressing signal for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal in an output simulation circuit; a section generating a loading signal, the duration of which may be equal to that of the noise suppressing signal or extended by an extension circuit in the event the array presents slower elements which may thus be read; and a section generating a circuit reset signal.
摘要翻译：电路包括产生用于异步地使读取相位的脉冲信号的部分; 产生预充电和检测可调节持续时间的信号的部分，用于控制从存储器读取数据并向输出缓冲器提供数据; 产生用于在加载到输出电路期间将输出缓冲器中的数据冻结的噪声抑制信号的部分，其持续时间恰好等于数据到存储器的输出电路的传播时间，如通过传播输出仿真电路中的数据模拟信号; 产生负载信号的部分，其持续时间可以等于噪声抑制信号的延迟，或者在阵列呈现较慢的元素，由此可以被读取的情况下由扩展电路扩展; 以及产生电路复位信号的部分。

15. 发明授权

US06307396B1 Low-consumption TTL-CMOS input buffer stage 失效
标题翻译：低功耗TTL-CMOS输入缓冲级
公开(公告)号：US06307396B1
公开(公告)日：2001-10-23
申请号：US09231130
申请日：1998-12-30
申请人： Jacopo Mulatti , Marco Maccarrone , Ignazio Martines , Rino Micheloni
发明人： Jacopo Mulatti , Marco Maccarrone , Ignazio Martines , Rino Micheloni
IPC分类号： H03K190185
CPC分类号： H03K19/0016
摘要： A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.
摘要翻译：低功耗TTL-CMOS输入缓冲级包括串联的反相器链，其串联在接收TTL逻辑电平的电信号的输入端和CMOS逻辑电平的输出再现电信号之间，并且在第一或电源电压基准和第二或地面参考。有利地，链中的第一反相器包括根据低功耗操作模式的激活信号选择到载物台的输送路径的装置。实质上，缓冲器的第一个反相器具有两个信号路径：一个用于正常操作，另一个用于低功耗操作。

16. 发明授权

US06204722B1 Electronic circuit for generating a stable voltage signal for polarizing during a reading step UPROM memory cells operating at low feed voltage 失效
标题翻译：用于在读取步骤期间产生用于偏振的稳定电压信号的电子电路在低馈电电压下工作的UPROM存储器单元
公开(公告)号：US06204722B1
公开(公告)日：2001-03-20
申请号：US09218796
申请日：1998-12-21
申请人： Marco Maccarrone , Stefano Commodaro , Marcelo Carrera , Andrea Ghilardelli
发明人： Marco Maccarrone , Stefano Commodaro , Marcelo Carrera , Andrea Ghilardelli
IPC分类号： G05F110
CPC分类号： G11C5/147 , G11C16/30 , G11C29/789
摘要： An electronic circuit generates a stable voltage signal for the polarization during a reading step of a UPROM redundancy cell incorporating at least one memory element of EPROM or Flash type, having at least one terminal to be polarized, and MOS transistors which connect such memory element to a low voltage power supply reference. The circuit includes a current mirror structure with a first control branch and a second output branch. The current mirror stricture includes a first series of MOS transistors (M2, M3, M4) in said first branch between the supply reference and a ground; and a second series of transistors (M5, M6, M7) in said second branch. The circuit also includes an input terminal connected to the gate terminal of a transistor of the first series of transistors and an output terminal corresponding to an interconnection node of the second series of transistors. The stable voltage is obtained through a current which passes through at least a pair of transistors of the second series.
摘要翻译：电子电路在包含至少一个EPROM或闪存型存储元件的UPROM冗余单元的读取步骤期间产生稳定的电压信号，其具有至少一个要极化的端子，以及将这种存储元件连接到低压电源参考。电路包括具有第一控制分支和第二输出分支的电流镜结构。电流反射镜狭窄包括在供电基准和地之间的所述第一分支中的第一系列MOS晶体管（M2，M3，M4）; 以及在所述第二分支中的第二系列晶体管（M5，M6，M7）。电路还包括连接到第一串联晶体管的晶体管的栅极端子的输入端子和对应于第二串联晶体管的互连节点的输出端子。通过穿过第二系列的至少一对晶体管的电流获得稳定的电压。

17. 发明授权

US6075750A Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory 有权
标题翻译：用于产生ATD信号以调节对非易失性存储器的访问的方法和电路
公开(公告)号：US6075750A
公开(公告)日：2000-06-13
申请号：US186497
申请日：1998-11-04
申请人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone , Matteo Zammattio
发明人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone , Matteo Zammattio
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C8/18
摘要： A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.
摘要翻译：一种方法和电路产生用于对半导体集成电子存储器件中的存储单元读取相位进行定时的脉冲同步信号（ATD）。在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD）。该方法包括将ATD信号复制到至少一对信号中，并且通过在ATD信号被恢复的端部处的分离的并行定时链传播这样的信号，链条交替活跃。

18. 发明授权

US6031761A Switching circuit having an output voltage varying between a reference voltage and a negative voltage 有权
标题翻译：开关电路具有在参考电压和负电压之间变化的输出电压
公开(公告)号：US6031761A
公开(公告)日：2000-02-29
申请号：US275255
申请日：1999-03-24
申请人： Andrea Ghilardelli , Stefano Ghezzi , Stefano Commodaro , Marco Maccarrone
发明人： Andrea Ghilardelli , Stefano Ghezzi , Stefano Commodaro , Marco Maccarrone
IPC分类号： G11C16/14 , G11C16/06
CPC分类号： G11C16/14
摘要： Switching circuit that receives a supply voltage, a reference voltage, a line adapted to carry a negative voltage and a control signal, the switching circuit capable of providing at an output a voltage alternatively equal to the reference voltage or to the voltage of the line in response to the control signal. The circuit includes a first MOSFET with a first electrode operationally connected to the line, a second electrode operationally connected to the output, and a control electrode, a second MOSFET with a first electrode operationally connected to the reference voltage, a second electrode operationally connected to the output, and a control electrode, and driving circuitry adapted to bring the control electrodes of the first and second MOSFETs respectively to the supply voltage and to the voltage of the line or, alternatively, to the voltage of the line and to the supply voltage, in response to the control signal.
摘要翻译：接收电源电压，参考电压，适于承载负电压的线路和控制信号的开关电路，所述开关电路能够在输出端提供交替地等于所述参考电压或所述线路的电压的电压响应控制信号。所述电路包括：第一电极，其具有可操作地连接到所述线路的第一电极，可操作地连接到所述输出端的第二电极;以及控制电极，具有可操作地连接到所述参考电压的第一电极的第二MOSFET，输出和控制电极以及适于将第一和第二MOSFET的控制电极分别连接到电源电压和线路电压的驱动电路，或者替代地将线路的电压和电源电压响应于控制信号。

19. 发明授权

US5955873A Band-gap reference voltage generator 失效
标题翻译：带隙基准电压发生器
公开(公告)号：US5955873A
公开(公告)日：1999-09-21
申请号：US960844
申请日：1997-10-30
申请人： Marco Maccarrone , Matteo Zammattio , Stefano Commodaro
发明人： Marco Maccarrone , Matteo Zammattio , Stefano Commodaro
IPC分类号： G05F3/26 , G05F3/30 , G05F3/16
CPC分类号： G05F3/30 , G05F3/26 , Y10S323/901 , Y10S323/907
摘要： A band-gap reference voltage generator comprises an operational amplifier comprising a first input and a second input, the first input being coupled to a first feedback network and the second input being coupled to a second feedback network both coupled to an output of the operational amplifier providing a reference voltage. The first feedback network contains an emitter-base junction of first bipolar junction transistor and the second feedback network contains an emitter-base junction of second bipolar junction transistor. A selectively activated current supply supplies a bias current to the operational amplifier, the current supply being deactivatable in a substantially zero power consumption operating condition for turning the reference voltage generator off. A start-up circuit activated upon start-up of the reference voltage generator for a fixed, prescribed time interval forces a start-up current to flow through the first bipolar junction transistor means.
摘要翻译：带隙参考电压发生器包括运算放大器，其包括第一输入端和第二输入端，第一输入端耦合到第一反馈网络，第二输入端耦合到第二反馈网络，二者耦合到运算放大器的输出端提供参考电压。第一反馈网络包含第一双极结晶体管的发射极 - 基极结，并且第二反馈网络包含第二双极结型晶体管的发射极 - 基极结。选择性地激活的电流源向运算放大器提供偏置电流，电流源可在基本为零的功耗操作条件下停用，用于使参考电压发生器关闭。在参考电压发生器启动固定的规定时间间隔时启动的启动电路迫使启动电流流过第一双极结型晶体管装置。

20. 发明授权

US5886925A Read circuit and method for nonvolatile memory cells with an equalizing structure 失效
标题翻译：具有均衡结构的非易失性存储单元的读取电路和方法
公开(公告)号：US5886925A
公开(公告)日：1999-03-23
申请号：US877922
申请日：1997-06-18
申请人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone
发明人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone
IPC分类号： G11C16/28 , G11C16/06
CPC分类号： G11C16/28
摘要： The read circuit presents a current mirror circuit including a first and second load transistor interposed between the supply line and a respective first and second output node. The first output node is connected to a cell to be read, the second output node is connected to a generating stage generating a reference current having a predetermined characteristic, and the size of the second load transistor is N times greater than the first load transistor. To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit presents a current balancing branch connected between the first output node and ground for generating an equalizing current presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.
摘要翻译：读取电路提供电流镜电路，其包括插入在电源线和相应的第一和第二输出节点之间的第一和第二负载晶体管。第一输出节点连接到要读取的单元，第二输出节点连接到产生具有预定特性的参考电流的发生级，并且第二负载晶体管的尺寸大于第一负载晶体管的N倍。为了即使在低电源电压并且没有初始不确定性的情况下也允许快速电池读取，均衡电路提供连接在第一输出节点和地之间的电流平衡支路，用于产生与参考值1 / N的比率的均衡电流电流在开始读数之前平衡电路。

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