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1. 发明授权

US5859797A Biasing circuit for UPROM cells with low voltage supply 失效
标题翻译：低压电源的UPROM单元的偏置电路
公开(公告)号：US5859797A
公开(公告)日：1999-01-12
申请号：US846753
申请日：1997-04-30
申请人： Marco Maccarrone , Jacopo Mulatti , Carla Maria Golla
发明人： Marco Maccarrone , Jacopo Mulatti , Carla Maria Golla
IPC分类号： G11C16/30 , G11C7/00
CPC分类号： G11C16/30
摘要： A circuit for generating biasing signals in reading of a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, as well as MOS transistors connecting the memory element with a reference low supply voltage comprises a voltage booster for generating a first voltage output signal to be applied to the control terminal of the memory element and a limitation network for the voltage signal connected to the output of the voltage booster. There is also provided a circuit portion for generating a second voltage output signal to be applied to the control terminal of one of the above mentioned transistors. This circuit portion comprises a timing section interlocked with the voltage booster of a section generating the second voltage signal.
摘要翻译：一种用于在读入包括EPROM或闪存类型的至少一个存储元件并具有要偏置的控制端子和导电端子的冗余UPROM单元的电路中产生偏置信号的电路，以及连接存储元件与参考电压的MOS晶体管低电源电压包括用于产生要施加到存储元件的控制端的第一电压输出信号的电压升压器和连接到升压器的输出的电压信号的限制网络。还提供了用于产生要施加到上述晶体管之一的控制端子的第二电压输出信号的电路部分。该电路部分包括与产生第二电压信号的部分的升压器互锁的定时部分。

2. 发明授权

US6153914A Output circuit for integrated circuits 有权
标题翻译：集成电路输出电路
公开(公告)号：US6153914A
公开(公告)日：2000-11-28
申请号：US170788
申请日：1998-10-13
申请人： Jacopo Mulatti , Stefano Zanardi , Carla Maria Golla , Armando Conci
发明人： Jacopo Mulatti , Stefano Zanardi , Carla Maria Golla , Armando Conci
IPC分类号： H01L21/8238 , H01L27/02 , H01L27/092 , H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H01L27/0928 , H01L27/0251 , H03K17/162 , H03K19/00361 , Y10S257/901
摘要： An output circuit for an integrated circuit, includes a first transistor and a second transistor connected in series between a first external voltage and a second external voltage external to the integrated circuit, respectively through first and second electrical connecting paths. The first transistor is for carrying an output line of the integrated circuit to the first external voltage, while the second transistor is for carrying the external line of the integrated circuit to the second external voltage. The second transistor is formed inside a first well of a first conductivity type contained inside a second well of a second conductivity type formed in a substrate of the first conductivity type. The second well of the second conductivity type is connected to the first external voltage through a third electrical connecting path distinct from the first electrical connecting path.
摘要翻译：用于集成电路的输出电路包括分别通过第一和第二电连接路径串联连接在集成电路外部的第一外部电压和第二外部电压之间的第一晶体管和第二晶体管。第一晶体管用于将集成电路的输出线传送到第一外部电压，而第二晶体管用于将集成电路的外部线路传送到第二外部电压。第二晶体管形成在形成在第一导电类型的衬底中的第二导电类型的第二阱内的第一导电类型的第一阱内。第二导电类型的第二阱通过与第一电连接路径不同的第三电连接路径连接到第一外部电压。

3. 发明授权

US5659509A Method for programming redundancy registers in a row redundancy integrated circuitry for a semiconductor memory device, and row redundancy integrated circuitry 失效
标题翻译：用于半导体存储器件的行冗余集成电路中的冗余寄存器的编程方法以及行冗余集成电路
公开(公告)号：US5659509A
公开(公告)日：1997-08-19
申请号：US391999
申请日：1995-02-16
申请人： Carla Maria Golla , Marco MacCarrone
发明人： Carla Maria Golla , Marco MacCarrone
IPC分类号： G11C29/00 , G11C29/04
CPC分类号： G11C29/789
摘要： A method for programming non-volatile row redundancy memory registers. Each register is associated with a respective pair of redundancy row and each one programmable to store in two subsets of a set of memory cells a pair of addresses of a respective pair of adjacent defective rows. Each memory register is supplied with row address signals and with a respective selection signal belonging to a set of column address signals. The method provides for: applying to the row address lines the address of a first defective row of the pair of adjacent defective rows; activating one of the selection signals for selecting the register which is to be programmed; applying to a further column address line a first logic level to select for programming in the selected memory register, a first subset of memory cells; enabling the programming of the address of the first defective row of the pair of adjacent defective rows into the first subset of memory cells; applying to at least a subset of the row address lines the address of the second defective row of the pair; applying to the further column line a second, opposite logic level to select for programming, in the selected memory register, at least a group of memory cells of the second subset of the two subsets of memory cells; and enabling the programming of the address of the second defective row of the pair of adjacent defective rows into the second subset of memory cells.
摘要翻译：一种用于编程非易失性行冗余存储器寄存器的方法。每个寄存器与相应的一对冗余行相关联，并且每个寄存器可编程以在一组存储器单元的两个子集中存储相应的一对相邻有缺陷行的一对地址。每个存储器寄存器被提供有行地址信号和属于一组列地址信号的相应选择信号。该方法提供：向行地址线应用该对相邻的有缺陷行的第一缺陷行的地址; 激活用于选择要编程的寄存器的选择信号之一; 向另一列地址线施加第一逻辑电平以选择用于在选择的存储器寄存器中编程存储器单元的第一子集; 使得能够将一对相邻的有缺陷行的第一缺陷行的地址编程到存储器单元的第一子集中; 向所述行地址线的至少一个子集施加所述对的所述第二缺陷行的地址; 在所选择的存储器寄存器中向所述另外的列线施加第二相反逻辑电平以选择用于在所述存储器单元的所述两个子集中的所述第二子集的至少一组存储器单元中进行编程; 并且使得能够将该对相邻的有缺陷行的第二有缺陷行的地址编程到存储器单元的第二子集中。

4. 发明授权

US06590247B2 MOS capacitor with wide voltage and frequency operating ranges 失效
标题翻译： MOS电容器具有宽电压和频率工作范围
公开(公告)号：US06590247B2
公开(公告)日：2003-07-08
申请号：US09916954
申请日：2001-07-27
申请人： Andrea Ghilardelli , Stefano Ghezzi , Carla Maria Golla
发明人： Andrea Ghilardelli , Stefano Ghezzi , Carla Maria Golla
IPC分类号： H01L2702
CPC分类号： H01L29/94
摘要： A MOS capacitor comprises a semiconductor substrate, a first well region of a first conductivity type formed in the substrate, at least one doped region formed in the first well region, and an insulated gate layer insulatively disposed over a surface of the first well region. The at least one doped region and the insulated gate layer respectively form a first and a second electrode of the capacitor. The first well region is electrically connected to the at least one doped region to be at a same electrical potential of the first terminal of the capacitor.
摘要翻译： MOS电容器包括半导体衬底，形成在衬底中的第一导电类型的第一阱区，形成在第一阱区中的至少一个掺杂区，以及绝缘栅层，绝缘地设置在第一阱区的表面上。所述至少一个掺杂区域和所述绝缘栅极层分别形成所述电容器的第一和第二电极。所述第一阱区电连接至所述至少一个掺杂区域以处于所述电容器的第一端子的相同电位。

5. 发明授权

US6064598A Switching circuit 有权
标题翻译：开关电路
公开(公告)号：US6064598A
公开(公告)日：2000-05-16
申请号：US275694
申请日：1999-03-24
申请人： Andrea Ghilardelli , Carla Maria Golla , Matteo Zammattio , Stefano Zanardi
发明人： Andrea Ghilardelli , Carla Maria Golla , Matteo Zammattio , Stefano Zanardi
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C16/12
摘要： A switching circuit comprising a supply voltage, a reference voltage, a line suitable to carry a negative voltage, an input for a control signal, suitable to supply to a first output node and to a second output node two voltages respectively equal to supply voltage and to line voltage or, alternatively, to line voltage and to supply voltage, in response to the control signal. There are first interrupting means, second interrupting means, third interrupting means, fourth interrupting means, the first and third interrupting means connected in series between the supply voltage and the line, the second and fourth interrupting means connected in series with each other and in parallel to first and third interrupting means, the first output node corresponding to common node between the first interrupting means and the third interrupting means, the second output node corresponding to common node between the second interrupting means and the fourth interrupting means, the control signal controlling first interrupting means and second interrupting means in such a way that when the first interrupting means are open, also the fourth interrupting means are open whereas the second interrupting means and third interrupting means are closed, connecting the first output node to line and the second output node to supply voltage, and vice versa when the first interrupting means are closed, also fourth interrupting means are closed whereas the second interrupting means and third interrupting means are open, connecting the first output node to supply voltage and the second output node to line.
摘要翻译：一种开关电路，包括电源电压，参考电压，适于承载负电压的线路，用于控制信号的输入端，适于向第一输出节点和第二输出节点提供分别等于电源电压的两个电压和或者作为线路电压，并且响应于控制信号而提供电压。第一中断装置，第二中断装置，第三中断装置，第四中断装置，串联连接在电源电压和线路之间的第一和第三中断装置，第二和第四中断装置彼此串联并联对于第一和第三中断装置，对应于第一中断装置和第三中断装置之间的公共节点的第一输出节点，对应于第二中断装置和第四中断装置之间的公共节点的第二输出节点，控制信号中断装置和第二中断装置，使得当第一中断装置打开时，第四中断装置也打开，而第二中断装置和第三中断装置关闭，将第一输出节点连接到线路，第二输出节点提供电压，反之亦然，当第一次中断时 ns闭合，第四中断装置闭合，而第二中断装置和第三中断装置断开，将第一输出节点连接到电源电压，将第二输出节点连接到线路。

6. 发明授权

US5768115A Voltage booster with an acceleration circuit 失效
标题翻译：带加速电路的升压器
公开(公告)号：US5768115A
公开(公告)日：1998-06-16
申请号：US855922
申请日：1997-05-14
申请人： Luigi Pascucci , Silvia Padoan , Carla Maria Golla
发明人： Luigi Pascucci , Silvia Padoan , Carla Maria Golla
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , H02M3/07 , H02M3/18 , G05F1/40
CPC分类号： H02M3/07 , G11C5/145
摘要： A voltage booster comprising a charge pump for generating a boost voltage over a boost line. The booster comprises a comparator which is supplied by a voltage divider with a voltage proportional to the boost voltage, and by a reference source with a low reference voltage, and which, depending on the outcome of the comparison, enables or disables the charge pump. A voltage limiter is connected between the boost line and ground; and a acceleration circuit accelerates the voltage increase on the acceleration line following low-power operation in which the paths toward ground are interrupted for reducing consumption.
摘要翻译：一种升压器，包括用于在升压线上产生升压电压的电荷泵。升压器包括由分压器提供的具有与升压电压成比例的电压的比较器和具有低参考电压的参考源，并且根据比较的结果，启用或禁用电荷泵。升压线和地之间连接一个限压器; 并且加速电路在低功率运行之后加速加速线上的电压增加，其中朝向地面的路径被中断以减少消耗。

7. 发明授权

US5815464A Address transition detection circuit 失效
标题翻译：地址转换检测电路
公开(公告)号：US5815464A
公开(公告)日：1998-09-29
申请号：US811869
申请日：1997-03-05
申请人： Carla Maria Golla , Matteo Zammattio , Stefano Zanardi
发明人： Carla Maria Golla , Matteo Zammattio , Stefano Zanardi
IPC分类号： G11C8/18 , H03K5/1534 , G11C7/00
CPC分类号： H03K5/1534 , G11C8/18
摘要： An address transition detection circuit having a number of cells supplied with respective address signals and outputs connected in a wired NOR configuration to generate a pulse signal on detecting transitions of their respective address signals. The pulse signal is supplied to a source stage for generating an address transition signal having a first and second switching edge on receiving the pulse signal. The source stage has a monostable stage for generating an end-of-transition signal with a predetermined delay following reception of the pulse signal; and an output stage connected to the cells and to the monostable stage, which generates the first switching edge of the address transition signal on receiving the pulse signal, and the second switching edge on receiving the end-of-transition signal. The monostable stage presents a compensating structure for maintaining the delay in the switching of the end-of-transition signal despite variations in temperature and supply voltage.
摘要翻译：一种地址转换检测电路，其具有提供有相应地址信号的单元的数量，并且以线性NOR配置连接的输出，以在检测各自地址信号的转变时产生脉冲信号。脉冲信号被提供给源级，用于在接收脉冲信号时产生具有第一和第二开关沿的地址转换信号。源级具有用于在接收到脉冲信号之后以预定延迟产生转换终止信号的单稳态级; 以及连接到单元和单稳态级的输出级，其在接收到脉冲信号时产生地址转换信号的第一开关沿，并且在接收到转换终止信号时产生第二开关沿。单稳态阶段提供了一种补偿结构，用于尽管温度和电源电压有变化，仍保持转换终止信号的切换延迟。

8. 发明授权

US5717642A Load signal generating method and circuit for nonvolatile memories 失效
标题翻译：用于非易失性存储器的负载信号产生方法和电路
公开(公告)号：US5717642A
公开(公告)日：1998-02-10
申请号：US803915
申请日：1997-02-25
申请人： Luigi Pascucci , Carla Maria Golla
发明人： Luigi Pascucci , Carla Maria Golla
IPC分类号： G11C5/14 , G11C7/22 , G11C16/32 , G11C7/00
CPC分类号： G11C16/32 , G11C5/143 , G11C7/22
摘要： A circuit for generating data load pulses of variable length as required includes a source for supplying a short load signal, and a delay element for generating longer pulses as of the short load signal. A static operating mode is provided wherein a load pulse is generated and maintained throughout static operation or as long as critical conditions (standby state, low voltage) persist. An extended pulse is always generated on exiting static operating mode; and the delay element may be disabled by a command when extended timing is not required.
摘要翻译：根据需要产生可变长度的数据负载脉冲的电路包括用于提供短负载信号的源和用于从短负载信号产生较长脉冲的延迟元件。提供静态操作模式，其中在静态操作期间或只要临界状态（待机状态，低电压）持续存在，就产生和维持负载脉冲。总是在退出静态工作模式时产生扩展脉冲; 并且当不需要扩展定时时，延迟元件可能被命令禁用。

9. 发明授权

US6144589A Boosting circuit, particularly for a memory device 有权
标题翻译：升压电路，特别是用于存储器件
公开(公告)号：US6144589A
公开(公告)日：2000-11-07
申请号：US186758
申请日：1998-11-05
申请人： Rino Micheloni , Giovanni Campardo , Donato Ferrario , Carla Maria Golla
发明人： Rino Micheloni , Giovanni Campardo , Donato Ferrario , Carla Maria Golla
IPC分类号： G11C8/08 , G11C8/10 , G11C16/08 , G11C7/00
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10
摘要： A boosting circuit supplied by a first voltage level and a second voltage level, and having an output line capable of taking a third voltage level, the circuit having at least two distinct circuits for generating the third voltage level, the at least two circuits selectively activatable for generating the third voltage level and selectively coupleable to the output line.
摘要翻译：由第一电压电平和第二电压电平提供的升压电路，并具有能够获得第三电压电平的输出线，所述电路具有用于产生第三电压电平的至少两个不同的电路，所述至少两个电路可选择地激活用于产生第三电压电平并选择性地耦合到输出线。

10. 发明授权

US6097213A Switching circuit with an output voltage changing among four possible values 有权
标题翻译：输出电压在四个可能值之间变化的开关电路
公开(公告)号：US6097213A
公开(公告)日：2000-08-01
申请号：US275691
申请日：1999-03-24
申请人： Andrea Ghilardelli , Carla Maria Golla , Matteo Zammattio , Stefano Zanardi
发明人： Andrea Ghilardelli , Carla Maria Golla , Matteo Zammattio , Stefano Zanardi
IPC分类号： G11C5/14 , G11C16/30 , H03K19/0948
CPC分类号： G11C16/30 , G11C5/14 , G11C5/143
摘要： Switching circuit comprising a reference voltage, an input voltage, suitable to assume alternatively a negative value or a value equal to said reference voltage, an output node, suitable to assume selectively three possible voltage values equal to a supply voltage, to the reference voltage, to the input voltage or, alternatively, to be kept floating, in response to a first, a second, a third, a fourth, a fifth, a sixth control logic signal, switching between the supply voltage and the reference voltage.
摘要翻译：开关电路包括参考电压，适于替代地假定为负值或等于所述参考电压的输入电压;输出节点，适于选择等于电源电压的三个可能的电压值与参考电压，响应于第一，第二，第三，第四，第五，第六，第六，第五，第六控制逻辑信号，在电源电压和参考电压之间切换，或者备选地保持浮置。

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