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1. 发明授权

US5805500A Circuit and method for generating a read reference signal for nonvolatile memory cells 失效
标题翻译：用于产生用于非易失性存储单元的读取参考信号的电路和方法
公开(公告)号：US5805500A
公开(公告)日：1998-09-08
申请号：US877921
申请日：1997-06-18
申请人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone
发明人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone
IPC分类号： G11C16/28 , G11C16/06
CPC分类号： G11C16/28
摘要： The current flowing through a cell to be read, forming part of a nonvolatile memory array and presenting a characteristic with a predetermined slope, is amplified N times and compared with a reference current presenting a two portion characteristic: a first portion extending between a predetermined threshold value and a trigger value, and presenting a slope equal to that of the memory cell characteristic, and a second portion extending from the trigger value, and presenting a slope amplified N times with respect to that of the cell characteristic and therefore equal to the amplified slope of the cell.
摘要翻译：流过待读取的单元的电流，形成非易失性存储器阵列的一部分并呈现具有预定斜率的特性，被放大N倍，并与呈现两部分特性的参考电流进行比较：在预定阈值之间延伸的第一部分值和触发值，并且呈现与存储器单元特性相同的斜率，以及从触发值延伸的第二部分，并且呈现相对于单元特性的N倍的斜率，因此等于放大的细胞斜率

2. 发明授权

US6075750A Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory 有权
标题翻译：用于产生ATD信号以调节对非易失性存储器的访问的方法和电路
公开(公告)号：US6075750A
公开(公告)日：2000-06-13
申请号：US186497
申请日：1998-11-04
申请人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone , Matteo Zammattio
发明人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone , Matteo Zammattio
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C8/18
摘要： A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.
摘要翻译：一种方法和电路产生用于对半导体集成电子存储器件中的存储单元读取相位进行定时的脉冲同步信号（ATD）。在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD）。该方法包括将ATD信号复制到至少一对信号中，并且通过在ATD信号被恢复的端部处的分离的并行定时链传播这样的信号，链条交替活跃。

3. 发明授权

US5886925A Read circuit and method for nonvolatile memory cells with an equalizing structure 失效
标题翻译：具有均衡结构的非易失性存储单元的读取电路和方法
公开(公告)号：US5886925A
公开(公告)日：1999-03-23
申请号：US877922
申请日：1997-06-18
申请人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone
发明人： Giovanni Campardo , Rino Micheloni , Marco Maccarrone
IPC分类号： G11C16/28 , G11C16/06
CPC分类号： G11C16/28
摘要： The read circuit presents a current mirror circuit including a first and second load transistor interposed between the supply line and a respective first and second output node. The first output node is connected to a cell to be read, the second output node is connected to a generating stage generating a reference current having a predetermined characteristic, and the size of the second load transistor is N times greater than the first load transistor. To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit presents a current balancing branch connected between the first output node and ground for generating an equalizing current presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.
摘要翻译：读取电路提供电流镜电路，其包括插入在电源线和相应的第一和第二输出节点之间的第一和第二负载晶体管。第一输出节点连接到要读取的单元，第二输出节点连接到产生具有预定特性的参考电流的发生级，并且第二负载晶体管的尺寸大于第一负载晶体管的N倍。为了即使在低电源电压并且没有初始不确定性的情况下也允许快速电池读取，均衡电路提供连接在第一输出节点和地之间的电流平衡支路，用于产生与参考值1 / N的比率的均衡电流电流在开始读数之前平衡电路。

4. 发明授权

US06157225A Driving circuit with three output levels, one output level being a boosted level 有权
标题翻译：驱动电路具有三个输出电平，一个输出电平为提升电平
公开(公告)号：US06157225A
公开(公告)日：2000-12-05
申请号：US234016
申请日：1999-01-19
申请人： Rino Micheloni , Giovanni Campardo , Marco Maccarrone , Maurizio Branchetti
发明人： Rino Micheloni , Giovanni Campardo , Marco Maccarrone , Maurizio Branchetti
IPC分类号： G11C8/08 , H03K19/0185 , H03K17/10
CPC分类号： H03K19/018585 , G11C8/08
摘要： A driving circuit supplied by a supply voltage and a reference voltage, generates an output signal and comprises a first circuit adapted to selectively couple the output signal to the reference voltage or to an internal voltage line internal to the driving circuit in response to a first control signal. The driving circuit also includes a switching circuit adapted to selectively couple the internal voltage line to the supply voltage. A boosting circuit is connected to the internal voltage line and is adapted to bring the internal voltage line to a boosted voltage. The switching circuit and the boosting circuit are controlled by a second control signal to be alternatively activatable, in such a way to bring the internal voltage line either to the supply voltage or to the boosted voltage.
摘要翻译：由电源电压和参考电压提供的驱动电路产生输出信号，并且包括适于选择性地将输出信号耦合到参考电压的第一电路或响应于第一控制的驱动电路内部的内部电压线信号。驱动电路还包括适于选择性地将内部电压线耦合到电源电压的开关电路。升压电路连接到内部电压线，并且适于使内部电压线达到升压电压。开关电路和升压电路由第二控制信号控制，以备可激活的方式，以使内部电压线达到供电电压或升压电压。

5. 发明授权

US06307396B1 Low-consumption TTL-CMOS input buffer stage 失效
标题翻译：低功耗TTL-CMOS输入缓冲级
公开(公告)号：US06307396B1
公开(公告)日：2001-10-23
申请号：US09231130
申请日：1998-12-30
申请人： Jacopo Mulatti , Marco Maccarrone , Ignazio Martines , Rino Micheloni
发明人： Jacopo Mulatti , Marco Maccarrone , Ignazio Martines , Rino Micheloni
IPC分类号： H03K190185
CPC分类号： H03K19/0016
摘要： A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.
摘要翻译：低功耗TTL-CMOS输入缓冲级包括串联的反相器链，其串联在接收TTL逻辑电平的电信号的输入端和CMOS逻辑电平的输出再现电信号之间，并且在第一或电源电压基准和第二或地面参考。有利地，链中的第一反相器包括根据低功耗操作模式的激活信号选择到载物台的输送路径的装置。实质上，缓冲器的第一个反相器具有两个信号路径：一个用于正常操作，另一个用于低功耗操作。

6. 发明授权

US06266222B1 ESD protection network for circuit structures formed in a semiconductor 有权
标题翻译：用于在半导体中形成的电路结构的ESD保护网络
公开(公告)号：US06266222B1
公开(公告)日：2001-07-24
申请号：US09223621
申请日：1998-12-30
申请人： Paolo Colombo , Jacopo Mulatti , Roberto Annunziata , Giovanni Campardo , Marco Maccarrone
发明人： Paolo Colombo , Jacopo Mulatti , Roberto Annunziata , Giovanni Campardo , Marco Maccarrone
IPC分类号： H02H904
CPC分类号： H01L27/0259 , H01L27/0251
摘要： An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply having a respective primary ground, and from at least one secondary voltage supply having a respective secondary ground. This network includes a first ESD protection element for an input stage of the circuit structure; a second ESD protection element for an output stage of the circuit structure, the first and second protection elements having an input/output pad of the integrated circuit structure in common; a first ESD protection element between the primary supply and the primary ground; and a second ESD protection element between the secondary supply and the secondary ground.
摘要翻译： ESD保护网络保护集成在半导体衬底中的CMOS电路结构。电路结构包括形成在相应的衬底部分中的分立电路块，它们彼此电绝缘并且由至少一个具有各自的初级接地的初级电压源以及至少一个具有相应次级接地的次级电压源独立供电。该网络包括用于电路结构的输入级的第一ESD保护元件; 用于所述电路结构的输出级的第二ESD保护元件，所述第一和第二保护元件具有所述集成电路结构的输入/输出焊盘; 主要供电和主地面之间的第一个ESD保护元件; 以及在次级电源和次级接地之间的第二ESD保护元件。

7. 发明授权

US08582364B2 Fast programming memory device 有权
公开(公告)号：US08582364B2
公开(公告)日：2013-11-12
申请号：US13155347
申请日：2011-06-07
申请人： Marco Maccarrone , Giuseppe Giannini , Demetrio Pellicone
发明人： Marco Maccarrone , Giuseppe Giannini , Demetrio Pellicone
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G06F1/28 , G06F3/0619 , G06F3/0625 , G06F3/0653 , G06F3/0688 , G06F12/0802 , G06F13/4282 , G06F2212/222 , G06F2213/0032 , G11C16/0483 , G11C16/14 , G11C16/26 , G11C16/28 , G11C16/30 , Y02D10/14 , Y02D10/151
摘要： In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.

8. 发明申请

US20110235411A1 FAST PROGRAMMING MEMORY DEVICE 有权
标题翻译：快速编程存储器件
公开(公告)号：US20110235411A1
公开(公告)日：2011-09-29
申请号：US13155347
申请日：2011-06-07
申请人： Marco Maccarrone , Giuseppe Giannini , Demetrio Pellicone
发明人： Marco Maccarrone , Giuseppe Giannini , Demetrio Pellicone
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G06F1/28 , G06F3/0619 , G06F3/0625 , G06F3/0653 , G06F3/0688 , G06F12/0802 , G06F13/4282 , G06F2212/222 , G06F2213/0032 , G11C16/0483 , G11C16/14 , G11C16/26 , G11C16/28 , G11C16/30 , Y02D10/14 , Y02D10/151
摘要： In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.
摘要翻译：在包括存储器单元矩阵的存储器件的实施例中，其中存储器单元布置在多个存储器单元串中，每个存储单元串包括至少两个串联的存储器单元，至少两个存储器单元串的组被连接到并且其中所述存储器单元适于被编程为至少第一编程状态和第二编程状态，存储数据的方法包括利用用于写入数据的每个存储器单元串的单个存储器单元，其中所述利用包括使单个存储器单元进入第二编程状态，所述串的剩余存储单元保持在第一编程状态。

9. 发明授权

US5650671A Charge pump circuit 失效
标题翻译：电荷泵电路
公开(公告)号：US5650671A
公开(公告)日：1997-07-22
申请号：US379689
申请日：1995-01-27
申请人： Luigi Pascucci , Marco Maccarrone , Silvia Padoan
发明人： Luigi Pascucci , Marco Maccarrone , Silvia Padoan
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , H02M3/07 , H02M3/18
CPC分类号： H02M3/07 , G11C5/145
摘要： A charge pump circuit including a number of pull-up stages connected in parallel with one another between a reference potential line and an output line. Each stage includes a capacitor having a first terminal connected to a charging and discharging node, and a second terminal connected to a pull-up node for switching between a first charging operating phase and a second charge transferring operating phase. The charging and discharging node is connected to the supply line via a charging transistor having a control terminal connected to a high-voltage bias node formed by the adjacent stage in the opposite operating phase, for charging the capacitor substantially up to the supply voltage.
摘要翻译：一种电荷泵电路，包括在参考电位线和输出线之间彼此并联连接的多个上拉级。每个级包括具有连接到充电和放电节点的第一端子的电容器，以及连接到上拉节点的第二端子，用于在第一充电操作阶段和第二充电转移操作阶段之间切换。充电和放电节点通过充电晶体管连接到电源线，该充电晶体管具有在相反的工作阶段中由相邻级形成的高压偏置节点连接的控制端子，用于对电容器充电至基本上达到电源电压。

10. 发明授权

US5594703A End-of-count detecting device for nonvolatile memories 失效
标题翻译：非易失性存储器的计数结束检测装置
公开(公告)号：US5594703A
公开(公告)日：1997-01-14
申请号：US365510
申请日：1994-12-28
申请人： Marco Olivo , Marco Maccarrone
发明人： Marco Olivo , Marco Maccarrone
IPC分类号： G11C17/00 , G11C16/04 , H03K21/38 , G11C8/00
CPC分类号： H03K21/38
摘要： An end-of-count detecting device for nonvolatile memories, comprising a decoder in the form of a wired OR structure of a number of transistors of the same type, the gate terminals of which are fed with a count signal generated by a counter element and having a predetermined end-of-count value to be detected. A load, which may be static, pseudo-dynamic or dynamic, is provided between the common node of the decoder transistors and a reference potential line; and the decoder output formed by the common node assumes a different logic level according to whether or not the end-of-count value coded by the wired OR structure is reached. A number of wired OR structures may be arranged side by side with an array of transistors for detecting a number of end-of-count values of the same counter element.
摘要翻译：一种用于非易失性存储器的计数结束检测装置，包括具有相同类型的多个晶体管的有线OR结构形式的解码器，其栅极端被馈送由计数器元件产生的计数信号，具有要检测的预定计数结束值。在解码晶体管的公共节点和参考电位线之间提供可以是静态的，伪动态的或动态的负载; 并且由公共节点形成的解码器输出根据是否达到由有线OR结构编码的计数结束值而呈现不同的逻辑电平。多个有线OR结构可以并排布置有用于检测相同计数器元件的计数结束值的数量的晶体管阵列。

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