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11. 发明授权

US07826291B2 Precharge and evaluation phase circuits for sense amplifiers 有权
标题翻译：读出放大器的预充电和评估相位电路
公开(公告)号：US07826291B2
公开(公告)日：2010-11-02
申请号：US12174307
申请日：2008-07-16
申请人： Lorenzo Bedarida , Fabio Tassan Caser , Mauro Chinosi , Donato Ferrario
发明人： Lorenzo Bedarida , Fabio Tassan Caser , Mauro Chinosi , Donato Ferrario
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/08 , G11C16/28
摘要： A precharge and evaluation circuit for a memory sense amplifier includes a first precharge-phase transistor having a source coupled to a power-supply potential, a gate coupled to a precharge control line, and a drain. A second precharge-phase transistor has a drain coupled to the drain of the first precharge-phase transistor, a source, and a gate coupled to the source through a feedback circuit. A first read-phase transistor has a source coupled to the power-supply potential, and a gate and drain coupled to a comparator. A second read-phase transistor has a drain coupled to the drain of the first read-phase transistor, a source coupled to the source of the second precharge-phase transistor, and a gate coupled to the source of the second read-phase transistor through a feedback circuit. A column decoder is coupled to the sources of the second precharge-phase and second read-phase transistors.
摘要翻译：用于存储读出放大器的预充电和评估电路包括具有耦合到电源电位的源极的第一预充电相晶体管，耦合到预充电控制线的栅极和漏极。第二预充电相晶体管具有耦合到第一预充电相晶体管的漏极的漏极，源极和通过反馈电路耦合到源极的栅极。第一读取相晶体管具有耦合到电源电位的源极，以及耦合到比较器的栅极和漏极。第二读取相位晶体管具有耦合到第一读取相位晶体管的漏极的漏极，耦合到第二预充电相位晶体管的源极的栅极，以及耦合到第二读取相位晶体管的源极的栅极，一个反馈电路。列解码器耦合到第二预充电相位和第二读相晶体管的源极。

12. 发明申请

US20100014370A1 PRECHARGE AND EVALUATION PHASE CIRCUITS FOR SENSE AMPLIFIERS 有权
标题翻译：用于感知放大器的预处理和评估相位电路
公开(公告)号：US20100014370A1
公开(公告)日：2010-01-21
申请号：US12174307
申请日：2008-07-16
申请人： Lorenzo Bedarida , Fabio Tassan Caser , Mauro Chinosi , Donato Ferrario
发明人： Lorenzo Bedarida , Fabio Tassan Caser , Mauro Chinosi , Donato Ferrario
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/08 , G11C16/28
摘要： A precharge and evaluation circuit for a memory sense amplifier includes a first precharge-phase transistor having a source coupled to a power-supply potential, a gate coupled to a precharge control line, and a drain. A second precharge-phase transistor has a drain coupled to the drain of the first precharge-phase transistor, a source, and a gate coupled to the source through a feedback circuit. A first read-phase transistor has a source coupled to the power-supply potential, and a gate and drain coupled to a comparator. A second read-phase transistor has a drain coupled to the drain of the first read-phase transistor, a source coupled to the source of the second precharge-phase transistor, and a gate coupled to the source of the second read-phase transistor through a feedback circuit. A column decoder is coupled to the sources of the second precharge-phase and second read-phase transistors.
摘要翻译：用于存储读出放大器的预充电和评估电路包括具有耦合到电源电位的源极的第一预充电相晶体管，耦合到预充电控制线的栅极和漏极。第二预充电相晶体管具有耦合到第一预充电相晶体管的漏极的漏极，源极和通过反馈电路耦合到源极的栅极。第一读取相晶体管具有耦合到电源电位的源极，以及耦合到比较器的栅极和漏极。第二读取相位晶体管具有耦合到第一读取相位晶体管的漏极的漏极，耦合到第二预充电相位晶体管的源极的栅极，以及耦合到第二读取相位晶体管的源极的栅极，一个反馈电路。列解码器耦合到第二预充电相位和第二读相晶体管的源极。

13. 发明授权

US07522463B2 Sense amplifier with stages to reduce capacitance mismatch in current mirror load 有权
标题翻译：具有阶段的感应放大器，以减少电流镜像负载中的电容失配
公开(公告)号：US07522463B2
公开(公告)日：2009-04-21
申请号：US11652770
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre′
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre′
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
摘要翻译：一种用于读取存储器单元状态的读出放大器电路。在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上不受由第一和第二级的瞬态特性提供的电容电流分量的影响。

14. 发明授权

US07177198B2 Compensated method to implement a high voltage discharge phase after erase pulse in a flash memory device 有权
标题翻译：补偿方法在闪存器件中擦除脉冲后实现高电压放电相位
公开(公告)号：US07177198B2
公开(公告)日：2007-02-13
申请号：US11123979
申请日：2005-05-06
申请人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre′
发明人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre′
IPC分类号： G11C11/34
CPC分类号： G11C16/14
摘要： A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.
摘要翻译：一种闪速存储装置中的放电方法包括：在擦除操作之后启动存储单元的放电; 将第一放电电路耦合到栅极 - 体积电容器的第一板，以及将第二放电电路耦合到栅极 - 体积电容器的第二板，其中第一板表示存储单元的公共栅极节点，第二板表示存储器单元的批量源节点; 并将公共栅极节点和体源节点耦合到地，以提供完全放电。注入第一板的电流大约等于从第二板提取的电流。以这种方式，在没有复杂设计或限压器的情况下，栅极和体源电压的危险振荡消除，而不会在擦除操作之后不牺牲快速放电。因此，放电操作的可靠性显着提高。

15. 发明申请

US20060062063A1 Compensated method to implement a high voltage discharge phase after erase pulse in a flash memory device 有权
标题翻译：补偿方法在闪存器件中擦除脉冲后实现高电压放电相位
公开(公告)号：US20060062063A1
公开(公告)日：2006-03-23
申请号：US11123979
申请日：2005-05-06
申请人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre'
发明人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre'
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G11C16/14
摘要： A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.
摘要翻译：一种闪速存储装置中的放电方法包括：在擦除操作之后启动存储单元的放电; 将第一放电电路耦合到栅极 - 体积电容器的第一板，以及将第二放电电路耦合到栅极 - 体积电容器的第二板，其中第一板表示存储单元的公共栅极节点，第二板表示存储器单元的批量源节点; 并将公共栅极节点和体源节点耦合到地，以提供完全放电。注入第一板的电流大约等于从第二板提取的电流。以这种方式，在没有复杂设计或限压器的情况下，栅极和体源电压的危险振荡消除，而不会在擦除操作之后不牺牲快速放电。因此，放电操作的可靠性显着提高。

16. 发明授权

US08837252B2 Memory decoder circuit 有权
标题翻译：内存解码电路
公开(公告)号：US08837252B2
公开(公告)日：2014-09-16
申请号：US13485675
申请日：2012-05-31
申请人： Lorenzo Bedarida , Nicolas Zammit , Emmanuel Racape
发明人： Lorenzo Bedarida , Nicolas Zammit , Emmanuel Racape
IPC分类号： G11C11/00
CPC分类号： G11C8/10
摘要： A decoder circuit includes high voltage and low voltage transistors. The decoder circuit uses the high voltage transistors during modify operations to provide a high voltage, e.g., a boosted voltage, to memory cells to change memory cell status or perform other operations. The decoder circuit uses the low voltage transistors during read operations.
摘要翻译：解码器电路包括高压和低压晶体管。解码器电路在修改操作期间使用高压晶体管来向存储器单元提供高电压，例如升压电压，以改变存储器单元状态或执行其他操作。解码器电路在读取操作期间使用低电压晶体管。

17. 发明授权

US07864557B2 Flexible OTP sector protection architecture for flash memories 有权
标题翻译：灵活的OTP扇区保护架构，用于闪存
公开(公告)号：US07864557B2
公开(公告)日：2011-01-04
申请号：US11529158
申请日：2006-09-28
申请人： Riccardo Riva Reggiori , Lorenzo Bedarida , Giorgio Oddone , Fabio Tassan Caser
发明人： Riccardo Riva Reggiori , Lorenzo Bedarida , Giorgio Oddone , Fabio Tassan Caser
IPC分类号： G11C17/00
CPC分类号： G11C16/22 , G11C2216/26
摘要： A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.
摘要翻译：公开了一种用于保护具有多个块的存储器不被修改的方法和系统。该方法和系统包括提供与OTP单元耦合的多个一次可编程（OTP）单元和OTP单元逻辑。多个OTP单元的OTP单元对应于多个块的块的一部分。当OTP小区处于第一状态时，OTP小区允许修改块的部分，并且当OTP小区处于第二状态时永久地防止块的该部分的修改。 OTP单元逻辑使用多个OTP单元来选择与OTP单元相对应的块的该部分。当OTP单元处于第二状态时，块的这一部分是写保护的。

18. 发明授权

US07782695B2 Compensated current offset in a sensing circuit 有权
标题翻译：感测电路中的补偿电流偏移
公开(公告)号：US07782695B2
公开(公告)日：2010-08-24
申请号：US11652742
申请日：2007-01-12
申请人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
发明人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C7/02 , G11C7/067 , G11C16/26 , G11C2207/063
摘要： A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.
摘要翻译：具有电流偏移功能的感测电路。在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

19. 发明授权

US07561485B2 Sense architecture 有权
标题翻译：感觉架构
公开(公告)号：US07561485B2
公开(公告)日：2009-07-14
申请号：US11652771
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Simone Bartoli , Giorgio Bosisio
发明人： Gabriele Pelli , Lorenzo Bedarida , Simone Bartoli , Giorgio Bosisio
IPC分类号： G11C7/02
CPC分类号： G11C16/28
摘要： A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier, where the second bitline produces a second transient current that is equal to the first transient current. The sense amplifier enables the first and second transient currents to be canceled. According to the system disclosed herein, the state of a memory cell may be determined without being adversely affected by transient currents.
摘要翻译：公开了一种存储系统。在一个实施例中，存储器系统包括第一位线，其中第一位线产生第一瞬态电流。存储器系统还包括耦合到第一位线的读出放大器。存储器系统还包括耦合到读出放大器的第二位线，其中第二位线产生等于第一瞬态电流的第二瞬态电流。读出放大器能够消除第一和第二瞬态电流。根据本文公开的系统，可以确定存储器单元的状态而不受瞬态电流的不利影响。

20. 发明授权

US07158415B2 System for performing fast testing during flash reference cell setting 有权
标题翻译：在闪存参考单元设置期间执行快速测试的系统
公开(公告)号：US07158415B2
公开(公告)日：2007-01-02
申请号：US11089268
申请日：2005-03-24
申请人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
发明人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
IPC分类号： G11C16/10
CPC分类号： G11C29/028 , G11C16/04 , G11C29/24 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： An embedded circuit in a memory device is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells. An external test device programs at least one reference cell to a predetermined value. The embedded circuit uses the cell programmed by the external device as a comparative reference to program additional reference cells.
摘要翻译：使用存储器件中的嵌入式电路来代替外部测试装置来执行耗费时间的任务，例如参考单元设置期间的电压验证。外部测试装置将至少一个参考单元编程为预定值。嵌入式电路使用由外部设备编程的单元作为比较参考来编程附加参考单元。

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