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11. 发明授权

US07005874B2 Utilizing clock shield as defect monitor 有权
标题翻译：利用时钟屏蔽作为缺陷监视器
公开(公告)号：US07005874B2
公开(公告)日：2006-02-28
申请号：US10710222
申请日：2004-06-28
申请人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
发明人： John M. Cohn , Leah M. P. Pastel , Thomas G. Sopchak , David P. Vallett
IPC分类号： G01R31/02
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.
摘要翻译：公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。屏蔽与时钟信号接线相邻，接地线将屏蔽接地。屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

12. 发明授权

US08347260B2 Method of designing an integrated circuit based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage 有权
标题翻译：基于可制造性，测试覆盖和可选地诊断覆盖的组合来设计集成电路的方法
公开(公告)号：US08347260B2
公开(公告)日：2013-01-01
申请号：US12880228
申请日：2010-09-13
申请人： Kerry Bernstein , James A. Culp , Leah M. P. Pastel , Kirk D. Peterson , Norman J. Rohrer
发明人： Kerry Bernstein , James A. Culp , Leah M. P. Pastel , Kirk D. Peterson , Norman J. Rohrer
IPC分类号： G06F11/22
CPC分类号： G06F17/5045 , G06F2217/12 , Y02P90/265
摘要： Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.
摘要翻译：披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。或者，可以根据DFM修改建立集成电路的测试覆盖。或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。

13. 发明授权

US07484423B2 Integrated carbon nanotube sensors 失效
标题翻译：集成碳纳米管传感器
公开(公告)号：US07484423B2
公开(公告)日：2009-02-03
申请号：US11696370
申请日：2007-04-04
申请人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
发明人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
IPC分类号： G01B7/16 , G01L1/00 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , G01R31/2884 , H01L27/088 , H01L27/286 , H01L29/0673 , H01L29/78 , H01L51/0048 , H01L51/0512 , Y10S977/761 , Y10S977/762 , Y10S977/765
摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
摘要翻译：一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。此外，CNT FET适用于检测集成电路内的故障电路。

14. 发明授权

US07064570B2 Method for locating IDDQ defects using multiple controlled collapse chip connections current measurement on an automatic tester 失效
标题翻译：使用多个受控崩溃芯片连接在自动测试仪上进行电流测量来定位IDDQ缺陷的方法
公开(公告)号：US07064570B2
公开(公告)日：2006-06-20
申请号：US10665321
申请日：2003-09-20
申请人： Patrick H. Buffet , Douglas C. Heaberlin , Leah M. P. Pastel , Yu H. Sun
发明人： Patrick H. Buffet , Douglas C. Heaberlin , Leah M. P. Pastel , Yu H. Sun
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2843 , G01R31/2853 , G01R31/3008 , G01R31/3012
摘要： A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.
摘要翻译：公开了一种用于改善I DDQ 缺陷测试中的信噪比的方法。集成电路被分成多个区域，并且每个区域由终端设置和限制。在集成电路内激活了一个DDQ 缺陷以产生缺陷电流。在提供给它的端子处测量在每个区域内产生的缺陷电流的量。基于每个区域上的I＆lt; DDQ＆lt; DDQ＆lt;＆gt;当前测量结果，创建I＆lt; DDQ＆gt;当前地图。通过分析当前地图，确定缺陷的存在和位置。基于确定，分离了I DDQ 缺陷。

15. 发明授权

US06677774B2 Method for locating IDDQ defects using multiple controlled collapse chip connections current measurement on an automatic tester 失效
标题翻译：使用多个受控崩溃芯片连接在自动测试仪上进行电流测量来定位IDDQ缺陷的方法
公开(公告)号：US06677774B2
公开(公告)日：2004-01-13
申请号：US09681917
申请日：2001-06-26
申请人： Patrick H. Buffet , Douglas C. Heaberlin , Leah M. P. Pastel , Yu H. Sun
发明人： Patrick H. Buffet , Douglas C. Heaberlin , Leah M. P. Pastel , Yu H. Sun
IPC分类号： G01R3126
CPC分类号： G01R31/2843 , G01R31/2853 , G01R31/3008 , G01R31/3012
摘要： A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.
摘要翻译：公开了一种用于提高IDDQ缺陷测试中的信噪比的方法。集成电路被分成多个区域，并且每个区域由终端设置和限制。激活IDDQ缺陷以在集成电路内产生IDDQ缺陷电流。在提供给它的端子处测量在每个区域内产生的IDDQ缺陷电流量。根据每个区域的IDDQ电流测量，创建一个IDDQ当前图。通过分析IDDQ当前图，确定缺陷的存在和位置。根据确定，IDDQ缺陷是孤立的。

16. 发明申请

US20080284459A1 Testing Using Independently Controllable Voltage Islands 审中-公开
标题翻译：使用独立可控电压岛进行测试
公开(公告)号：US20080284459A1
公开(公告)日：2008-11-20
申请号：US12185151
申请日：2008-08-04
申请人： Anne E. Gattiker , Phil Nigh , Leah M. P. Pastel , Steven F. Oakland , Jody VanHorn , Paul S. Zuchowski
发明人： Anne E. Gattiker , Phil Nigh , Leah M. P. Pastel , Steven F. Oakland , Jody VanHorn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318575 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands, each powered by a respective island source voltage, and a testing circuit, coupled to the voltage islands, and powered by a global source voltage that is always on during test, wherein each island source voltage may be independently controlled during test.
摘要翻译：一种电压岛结构，其中每个电压岛的源电压可以在基于扫描的测试期间独立地接通/关断或调节。该架构包括多个电压岛，每个电压岛由相应的岛源电压供电，以及耦合到电压岛的测试电路，并由在测试期间始终导通的全局源电压供电，其中每个岛源电压可以是在测试期间独立控制。

17. 发明授权

US07428675B2 Testing using independently controllable voltage islands 失效
标题翻译：使用独立可控电压岛测试
公开(公告)号：US07428675B2
公开(公告)日：2008-09-23
申请号：US10545961
申请日：2003-02-20
申请人： Anne E. Gattiker , Phil Nigh , Leah M. P. Pastel , Steven F. Oakland , Jody VanHorn , Paul S. Zuchowski
发明人： Anne E. Gattiker , Phil Nigh , Leah M. P. Pastel , Steven F. Oakland , Jody VanHorn , Paul S. Zuchowski
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318575 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands (102, 104), each powered by a respective island source voltage (VDDI1, VDDI2), and a testing circuit (116), coupled to the voltage islands, and powered by a global source voltage (Vg) that is always on during test, wherein each island source voltage may be independently controlled (106, 108) during test.
摘要翻译：一种电压岛结构，其中每个电压岛的源电压可以在基于扫描的测试期间独立地接通/关断或调节。该架构包括多个电压岛（102,104），每个电压岛由相应的岛源电压（VDDI 1，VDDI 2）供电，以及耦合到电压岛的测试电路（116），并由全局源在测试期间总是导通的电压（Vg），其中每个岛源电压可以在测试期间被独立地控制（106,108）。

18. 发明申请

US20080129324A1 Hot Switchable Voltage Bus for Iddq Current Measurements 审中-公开
标题翻译：可开关电压总线，用于Iddq电流测量
公开(公告)号：US20080129324A1
公开(公告)日：2008-06-05
申请号：US10595526
申请日：2003-11-05
申请人： Leah M. P. Pastel
发明人： Leah M. P. Pastel
IPC分类号： G01R31/30
CPC分类号： G01R31/3008
摘要： A voltage island system including a hot-switchable voltage bus for IDDQ current measurements. The voltage island system includes a plurality of voltage islands (V1, V2, . . . , Vn), a global power system, and a quiescent power system. The global power system includes a plurality of on-chip global header devices (H1, H2, . . . , Hn) for selectively providing a voltage VDDg to the plurality of voltage islands in response to global header control signals (x1, x2, . . . , xn), respectively. A global VDDg power supply provides power to the global header devices (H1, H2, . . . , Hn) via a VDDg power distribution grid/bus. The quiescent power system includes a plurality of on-chip quiescent header devices (H1q, H2q, . . . , Hnq) for selectively providing a quiescent voltage VDDq to the plurality of voltage islands in response to quiescent header control signals x1q, x2q, . . . , xnq, respectively. A quiescent VDDq power supply provides power to the quiescent header devices via a VDDq power distribution grid/bus.
摘要翻译：一个电压岛系统，包括用于IDDQ电流测量的热切换电压总线。电压岛系统包括多个电压岛（V 1，V 2，...，Vn），全球电力系统和静态电力系统。全球电力系统包括多个片上全局头部装置（H 1，H 2，...，Hn），用于响应于全局头部控制信号（x 1，...，H n）选择性地向多个电压岛提供电压VDDg， x 2，...，xn）。全局VDDg电源通过VDDg配电网/总线为全局总线设备（H 1，H 2，...，Hn）提供电源。静态电力系统包括多个片上静态头部装置（H 1 q，H 2 q，...，Hnq），用于响应于静态头部控制信号x而选择性地向多个电压岛提供静态电压VDDq 1 q，x 2 q，。。。，xnq。静态VDDq电源通过VDDq配电网/总线为静态接头设备供电。

19. 发明授权

US07093213B2 Method for designing an integrated circuit defect monitor 失效
标题翻译：设计集成电路缺陷监视器的方法
公开(公告)号：US07093213B2
公开(公告)日：2006-08-15
申请号：US10710940
申请日：2004-08-13
申请人： John M. Cohn , Leah M. P. Pastel
发明人： John M. Cohn , Leah M. P. Pastel
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/505
摘要： A method and system for designing a test structure. The method including: defining and placing test circuit pins in an integrated circuit design; routing one or more fat wires, each fat wire routed between a set of the test circuit pins; processing each fat wire into a continuous wire and one or more corresponding wire segments adjacent to the continuous wire, the continuous wire separated from the one or more corresponding wire segments by a space; and connecting the continuous wire and the one or more wire segments to circuit elements of a defect monitor scan chain, the circuit elements previously inserted into the integrated circuit design.
摘要翻译：一种用于设计测试结构的方法和系统。该方法包括：将集成电路设计中的测试电路引脚定义和放置; 布置一条或多条脂肪线，每条脂肪线在一组测试电路引脚之间布线; 将每个脂肪丝处理成连续的线和与所述连续线相邻的一个或多个对应的线段，所述连续线从所述一个或多个对应的线段与空间分离; 以及将连续线和一个或多个线段连接到缺陷监视器扫描链的电路元件，电路元件先前插入到集成电路设计中。

20. 发明授权

US07089138B1 Canary device for failure analysis 失效
标题翻译：金丝雀装置进行故障分析
公开(公告)号：US07089138B1
公开(公告)日：2006-08-08
申请号：US10906590
申请日：2005-02-25
申请人： Pierre J. Bouchard , Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , James A. Slinkman , David P. Vallett
发明人： Pierre J. Bouchard , Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , James A. Slinkman , David P. Vallett
IPC分类号： G06F11/00
CPC分类号： G01R31/2856 , G01R31/2831 , G01R31/318511 , G01R31/3187
摘要： A diagnostic system and method for testing an integrated circuit during fabrication thereof. The diagnostic system has at least one integrated circuit chip that has an electrical signature associated with it; a sacrificial circuit that is adjacent to the integrated circuit chip and has a known electrical signature associated with it and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit indicates that the integrated circuit chip is mis-designed. The diagnostic system further includes a semiconductor wafer that has a plurality of integrated circuit chips and a kerf area separating one integrated circuit chip from another integrated circuit chip. A mis-designed integrated circuit chip has abnormally functioning circuitry.
摘要翻译：一种在其制造期间测试集成电路的诊断系统和方法。诊断系统具有至少一个具有与其相关联的电特征的集成电路芯片; 牺牲电路，其与集成电路芯片相邻并且具有与其相关联的已知电气签名和故意错误设计的电路; 以及比较器，用于将集成电路芯片的电特征与牺牲电路的已知电特征进行比较，其中集成电路芯片的电特征中与牺牲电路的已知电气签名的匹配指示集成电路芯片设计错误。诊断系统还包括具有多个集成电路芯片的半导体晶片和将一个集成电路芯片与另一个集成电路芯片分离的切口区域。错误设计的集成电路芯片具有异常功能的电路。

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