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11. 发明授权

US06894351B2 Semiconductor device for electrostatic protection 有权
标题翻译：用于静电保护的半导体器件
公开(公告)号：US06894351B2
公开(公告)日：2005-05-17
申请号：US10329676
申请日：2002-12-27
申请人： Kazuhiko Okawa , Takayuki Saiki
发明人： Kazuhiko Okawa , Takayuki Saiki
IPC分类号： H01L29/749 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/74 , H01L27/01 , H01L31/111
CPC分类号： H01L27/0262 , H01L27/12 , H01L29/7436
摘要： The invention makes it possible to form thyristers and SCRs that show a good discharge efficiency upon application of static electricity in semiconductor devices using a SOI substrate. A semiconductor device is equipped with a connection terminal for connection with an external element, a dielectric substrate having a semiconductor layer formed therein, a first region of a first conductive type that is formed in the semiconductor layer and electrically connected to the connection terminal, a second region of a second conductive type that is formed in the semiconductor layer and electrically connected to the first region, a third region of the first conductive type that is formed adjacent to the second region in the semiconductor layer, and a fourth region of the second conductive type that is formed adjacent to the third region in the semiconductor layer.
摘要翻译：本发明使得可以形成在使用SOI衬底的半导体器件中施加静电时显示出良好的放电效率的晶体管和SCR。半导体器件配备有用于与外部元件连接的连接端子，其中形成有半导体层的电介质基板，形成在半导体层中并电连接到连接端子的第一导电类型的第一区域，第二导电类型的第二区域，形成在所述半导体层中并电连接到所述第一区域;所述第一导电类型的第三区域与所述半导体层中的所述第二区域相邻形成;以及第二区域，导电型，其形成在半导体层中与第三区相邻。

12. 发明授权

US06831334B2 Semiconductor device having electrostatic protection circuit and method of fabricating the same 失效
标题翻译：具有静电保护电路的半导体器件及其制造方法
公开(公告)号：US06831334B2
公开(公告)日：2004-12-14
申请号：US09866800
申请日：2001-05-30
申请人： Kazuhiko Okawa , Takayuki Saiki
发明人： Kazuhiko Okawa , Takayuki Saiki
IPC分类号： H01L2362
CPC分类号： H01L27/0255 , H01L27/0259
摘要： A semiconductor device including an electrostatic protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer. A plurality of salicide N-type MOS transistors isolated by a first diffusion region are formed on a semiconductor substrate of this semiconductor device. An NPN lateral bipolar transistor and a Zener diode are formed as an electrostatic protection circuit for these MOS transistors. The NPN lateral bipolar transistor includes a P-type well and a second diffusion region which is formed in a region isolated by two second isolation regions. The Zener diode is formed by the PN junction between the first diffusion region of the MOS transistor and a third diffusion region. The breakdown start voltage of the Zener diode is set to be lower than the breakdown start voltage of the MOS transistor. A fourth diffusion region which makes up a Schottky diode together with the silicide layer is further provided between the silicide layer and the third diffusion region.
摘要翻译：一种包括静电保护电路的半导体器件，能够防止电流通过硅化物层集中在热点上。在该半导体器件的半导体衬底上形成由第一扩散区隔离的多个自对准硅化物N型MOS晶体管。形成NPN横向双极晶体管和齐纳二极管作为这些MOS晶体管的静电保护电路。 NPN横向双极晶体管包括P型阱和形成在由两个第二隔离区域隔离的区域中的第二扩散区域。齐纳二极管由MOS晶体管的第一扩散区域和第三扩散区域之间的PN结形成。齐纳二极管的击穿启动电压设定为低于MOS晶体管的击穿开始电压。在硅化物层和第三扩散区之间进一步设置与硅化物层一起构成肖特基二极管的第四扩散区域。

13. 发明授权

US06671146B1 Electrostatic protection circuit and semiconductor integrated circuit using the same 失效
标题翻译：静电保护电路和半导体集成电路使用相同
公开(公告)号：US06671146B1
公开(公告)日：2003-12-30
申请号：US09646332
申请日：2000-12-19
申请人： Masami Hashimoto , Kazuhiko Okawa
发明人： Masami Hashimoto , Kazuhiko Okawa
IPC分类号： H02H900
CPC分类号： H01L27/0255
摘要： An electrostatic protection circuit of the present invention comprises: a first power supply terminal 1 to which a first voltage is applied; a second power supply terminal 2 to which a second voltage lower than the first voltage is applied; a first diode 12 connected in a reverse direction between the first and second power supply terminals; and a second diode 11 connected in a forward direction between the first and second power supply terminals. This configuration ensures that either one of the first and second diodes always operates in a forward direction to the static electricity applied between the first and second power supply terminals regardless of the polarity of the static electricity. Electrostatic charges therefore can be quickly absorbed through the diode in a forward direction.
摘要翻译：本发明的静电保护电路包括：施加第一电压的第一电源端子1; 施加低于第一电压的第二电压的第二电源端子2; 在第一和第二电源端子之间沿相反方向连接的第一二极管12; 以及在第一和第二电源端子之间沿正向连接的第二二极管11。这种配置确保了第一和第二二极管中的任何一个总是在与第一和第二电源端子之间施加的静电的正向方向上工作，而与静电的极性无关。因此，静电电荷可以通过二极管在正向方向上被快速吸收。

14. 发明申请

US20080224219A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080224219A1
公开(公告)日：2008-09-18
申请号：US12126473
申请日：2008-05-23
申请人： Takayuki SAIKI , Kazuhiko Okawa
发明人： Takayuki SAIKI , Kazuhiko Okawa
IPC分类号： H01L23/62
CPC分类号： H01L27/0288
摘要： A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.
摘要翻译：提供具有高性能电阻元件的半导体器件。在绝缘膜隔离的N型阱中，形成两个较高浓度的N型区域。还形成层间绝缘膜。在层间绝缘膜的多个开口中，在一个N型区域上形成具有多个电极的一个电极组，而在另一个N型区域上形成具有多个电极的第二电极组。两个N型区域之间的关系在岛状区域和围绕岛状物的环状区域之间。岛状区域和环状区域之间的N型阱的环状区域用作电阻R.因此，由于ESD等而过度施加的电荷的放电通道在一个N的周边（四个区域）中均匀地存在型区域。

15. 发明授权

US07394134B2 Semiconductor device with electrostatic discharge protection 有权
标题翻译：具有静电放电保护的半导体器件
公开(公告)号：US07394134B2
公开(公告)日：2008-07-01
申请号：US11095709
申请日：2005-03-31
申请人： Takayuki Saiki , Kazuhiko Okawa
发明人： Takayuki Saiki , Kazuhiko Okawa
IPC分类号： H01L23/62
CPC分类号： H01L27/0288
摘要： A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.
摘要翻译：提供具有高性能电阻元件的半导体器件。在绝缘膜隔离的N型阱中，形成两个较高浓度的N型区域。还形成层间绝缘膜。在层间绝缘膜的多个开口中，在一个N型区域上形成具有多个电极的一个电极组，而在另一个N型区域上形成具有多个电极的第二电极组。两个N型区域之间的关系在岛状区域和围绕岛状物的环状区域之间。岛状区域和环状区域之间的N型阱的环状区域用作电阻R.因此，由于ESD等而过度施加的电荷的放电通道在一个N的周边（四个区域）中均匀地存在型区域。

16. 发明授权

US06861705B2 Driver circuits and methods for manufacturing driver circuits 失效
标题翻译：用于制造驱动电路的驱动电路和方法
公开(公告)号：US06861705B2
公开(公告)日：2005-03-01
申请号：US09801025
申请日：2001-03-07
申请人： Satoshi Ito , Kazuhiko Okawa
发明人： Satoshi Ito , Kazuhiko Okawa
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8234 , H01L23/482 , H01L23/52 , H01L27/02 , H01L27/088 , H01L29/78
CPC分类号： H01L27/088 , H01L23/482 , H01L27/0207 , H01L2924/0002 , Y10S257/92 , H01L2924/00
摘要： Embodiments include a driver circuit that is suitable to prevent a delay in responding to an input of a drive signal and a method for manufacturing the same. Three contact holes are provided for each of the transistors Tr1-Tr4 for connecting the gate electrodes of the transistors to the signal lines Ls, Ls1-Ls4 that are separated from the transistors Tr1-Tr4 by the dielectric layer 14. As a result, the time for an input signal to reach the entire area of the gate electrodes becomes shorter and a response to an input of a drive signal becomes faster.
摘要翻译：实施例包括适于防止响应于驱动信号的输入的延迟的驱动器电路及其制造方法。为晶体管Tr1-Tr4的每一个提供三个接触孔，用于将晶体管的栅电极连接到由电介质层14与晶体管Tr1-Tr4分离的信号线Ls，Ls1-Ls4。结果，输入信号到达栅电极的整个区域的时间变短，并且对驱动信号的输入的响应变得更快。

17. 发明授权

US06653689B2 Semiconductor device having electrostatic protection circuit 有权
标题翻译：具有静电保护电路的半导体器件
公开(公告)号：US06653689B2
公开(公告)日：2003-11-25
申请号：US09873370
申请日：2001-06-05
申请人： Kazuhiko Okawa
发明人： Kazuhiko Okawa
IPC分类号： H01L2972
CPC分类号： H01L27/0262 , H01L27/0255 , H01L27/0288
摘要： A semiconductor device is provided with an electrostatic protection circuit that causes rapid breakdown of a Zener diode immediately after a static charge is applied, to discharge the static charge by a high-gain thyristor with good response characteristics, and that has a small surface area. When a static charge is applied, a Zener diode breaks down, which acts as a trigger to turn on a thyristor formed of an NPN bipolar transistor and a PNP bipolar transistor. The PNP bipolar transistor is formed of p-type, n-type, and p-type impurity diffusion regions formed in the thickness direction of the substrate and the Zener diode is formed of n-type and p-type impurity diffusion regions. An n-type impurity diffusion region is provided adjacent to a surface-layer p-type impurity diffusion region, and these p-type and n-type impurity diffusion regions are connected to a signal terminal through a silicide layer formed on the surfaces thereof.
摘要翻译：半导体器件设置有静电保护电路，其在施加静电荷之后立即引起齐纳二极管的快速击穿，以通过具有良好响应特性的高增益晶闸管对静电电荷进行放电，并具有小的表面积。当施加静电荷时，齐纳二极管发生故障，其作为触发器来接通由NPN双极晶体管和PNP双极晶体管形成的晶闸管。 PNP双极晶体管由在衬底的厚度方向上形成的p型，n型和p型杂质扩散区形成，并且齐纳二极管由n型和p型杂质扩散区形成。在表面层p型杂质扩散区域附近设置n型杂质扩散区域，这些p型杂质扩散区域和n型杂质扩散区域通过形成在其表面上的硅化物层与信号端子连接。

18. 发明授权

US06459139B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06459139B2
公开(公告)日：2002-10-01
申请号：US09727705
申请日：2000-12-04
申请人： Kunio Watanabe , Kazuhiko Okawa
发明人： Kunio Watanabe , Kazuhiko Okawa
IPC分类号： H01L2900
CPC分类号： H01L27/0251
摘要： The semiconductor device has an insulated-gate field-effect transistor (MOS transistor), a bipolar transistor, and a Zener diode. The MOS transistor is formed in a well of a first conductive type (p-type) and has a gate insulation layer, a gate electrode, side wall insulation layers, and second conductive type (n-type) of source and drain regions. The bipolar transistor has the drain region as a collector region, the well as a base region, and an n-type impurity-diffusion layer isolated from the drain region as an emitter region. The Zener diode is formed by the junction of an n-type impurity-diffusion layer continuous with the drain region and a p-type impurity-diffusion layer. The source and drain regions have a silicide layer formed on the surface thereof. A protection layer is formed on the surface of the n-type impurity-diffusion layer of the Zener diode.
摘要翻译：半导体器件具有绝缘栅场效应晶体管（MOS晶体管），双极晶体管和齐纳二极管。 MOS晶体管形成在第一导电类型（p型）的阱中，并且具有栅极绝缘层，栅电极，侧壁绝缘层和第二导电类型（n型）源极和漏极区。双极晶体管具有漏极区域作为集电极区域，阱作为基极区域，以及与漏极区域隔离的n型杂质扩散层作为发射极区域。齐纳二极管由与漏极区连续的n型杂质扩散层和p型杂质扩散层的结形成。源区和漏区在其表面上形成硅化物层。在齐纳二极管的n型杂质扩散层的表面上形成保护层。

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