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11. 发明申请

US20080150006A1 Using implanted poly-1 to improve charging protection in dual-poly process 有权
标题翻译：使用植入poly-1改善双重聚合过程中的充电保护
公开(公告)号：US20080150006A1
公开(公告)日：2008-06-26
申请号：US11724726
申请日：2007-03-16
申请人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
发明人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.
摘要翻译：本发明涉及在形成基于晶体管的存储器件中实现双重聚合工艺。该过程允许在沉积第二多晶硅层之后选择性地掺杂第一多晶硅层。该掺杂增加了第一多晶硅层的导电性，其可以实现针对多位磁芯阵列的更强鲁棒的充电保护和更均匀的电荷分布。

12. 发明授权

US07553727B2 Using implanted poly-1 to improve charging protection in dual-poly process 有权
标题翻译：使用植入poly-1改善双重聚合过程中的充电保护
公开(公告)号：US07553727B2
公开(公告)日：2009-06-30
申请号：US11724726
申请日：2007-03-16
申请人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
发明人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
IPC分类号： H01L21/8247
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.
摘要翻译：本发明涉及在形成基于晶体管的存储器件中实现双重聚合工艺。该过程允许在沉积第二多晶硅层之后选择性地掺杂第一多晶硅层。该掺杂增加了第一多晶硅层的导电性，其可以实现针对多位磁芯阵列的更强鲁棒的充电保护和更均匀的电荷分布。

13. 发明申请

US20080153269A1 Thin oxide dummy tiling as charge protection 有权
标题翻译：薄氧化虚拟平铺作为电荷保护
公开(公告)号：US20080153269A1
公开(公告)日：2008-06-26
申请号：US11645475
申请日：2006-12-26
申请人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
发明人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
IPC分类号： H01L21/20
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11568
摘要： The present invention pertains to a system and method for implementing dummy tiles in forming a memory device. The system and method involves forming at least a portion of a memory core array upon a semiconductor substrate comprising, forming STI structures in the substrate, depositing an oxide layer over the substrate, forming a first polysilicon layer over the oxide layer, doping the first polysilicon layer, forming a second polysilicon layer over the first polysilicon layer, patterning at least one memory core, patterning at least one dummy tile and performing back end processing.
摘要翻译：本发明涉及在形成存储器件时实现虚拟瓦片的系统和方法。该系统和方法包括在半导体衬底上形成存储芯阵列的至少一部分，包括：在衬底中形成STI结构，在衬底上沉积氧化层，在氧化物层上形成第一多晶硅层，掺杂第一多晶硅层，在第一多晶硅层上形成第二多晶硅层，图案化至少一个存储器芯，图案化至少一个虚拟贴片并执行后端处理。

14. 发明授权

US06436768B1 Source drain implant during ONO formation for improved isolation of SONOS devices 有权
标题翻译：在ONO形成期间的源极漏极注入，以改善SONOS器件的隔离
公开(公告)号：US06436768B1
公开(公告)日：2002-08-20
申请号：US09893279
申请日：2001-06-27
申请人： Jean Yee-Mei Yang , Mark T. Ramsbey , Emmanuil Manos Lingunis , Yider Wu , Tazrien Kamal , Yi He , Edward Hsia , Hidehiko Shiraiwa
发明人： Jean Yee-Mei Yang , Mark T. Ramsbey , Emmanuil Manos Lingunis , Yider Wu , Tazrien Kamal , Yi He , Edward Hsia , Hidehiko Shiraiwa
IPC分类号： H01L21336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L27/11568 , H01L29/66833
摘要： One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.
摘要翻译：本发明的一个方面涉及一种形成SONOS型非易失性半导体存储器件的方法，包括在半导体衬底上形成电荷俘获电介质的第一层; 在所述半导体衬底上的所述电荷俘获电介质的所述第一层上形成所述电荷俘获电介质的第二层; 可选地至少部分地在所述半导体衬底上的所述电荷俘获电介质的所述第二层上形成所述电荷俘获电介质的第三层; 任选地去除电荷俘获电介质的第三层; 在电荷俘获电介质上形成源极/漏极掩模; 将源极/漏极注入物通过电荷俘获电介质注入到半导体衬底中; 任选地去除电荷俘获电介质的第三层; 以及在半导体衬底上的电荷俘获电介质的第二层上形成电荷俘获电介质的第三层之一，在半导体衬底上的电荷俘获电介质的第二层上重整第三层电荷俘获电介质，或在电荷俘获电介质的第三层上形成附加材料。

15. 发明授权

US07163860B1 Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device 有权
标题翻译：在电荷捕获电介质闪速存储器件中形成具有降低的氢含量的栅堆叠间隔物和电荷储存材料的方法
公开(公告)号：US07163860B1
公开(公告)日：2007-01-16
申请号：US10430471
申请日：2003-05-06
申请人： Tazrien Kamal , Yun Wu , Mark Ramsbey , Jean Yee-Mei Yang , Arvind Halliyal , Rinji Sugino , Hidehiko Shiraiwa , Fred T K Cheung
发明人： Tazrien Kamal , Yun Wu , Mark Ramsbey , Jean Yee-Mei Yang , Arvind Halliyal , Rinji Sugino , Hidehiko Shiraiwa , Fred T K Cheung
IPC分类号： H01L21/8247
CPC分类号： H01L21/28282 , H01L29/7923 , Y10S438/954
摘要： The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.
摘要翻译：本发明在一个实施例中涉及一种用于制造电荷俘获电介质闪存器件的方法，该器件包括提供半导体衬底，该半导体衬底上形成有包括电荷俘获介电电荷存储层和覆盖电荷的控制栅电极俘获介电电荷存储层; 至少在所述栅叠层上形成氧化层; 以及在所述栅极堆叠上沉积间隔层，其中所述沉积步骤沉积相对于常规间隔物材料的氢含量具有降低的氢含量的间隔物材料。

16. 发明授权

US07023046B2 Undoped oxide liner/BPSG for improved data retention 有权
标题翻译：未掺杂氧化物衬垫/ BPSG，以改善数据保留
公开(公告)号：US07023046B2
公开(公告)日：2006-04-04
申请号：US10617450
申请日：2003-07-11
申请人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
发明人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/31612 , H01L21/31625 , H01L27/115 , H01L29/511
摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.
摘要翻译：具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在相同的沉积室。

17. 发明授权

US07098546B1 Alignment marks with salicided spacers between bitlines for alignment signal improvement 有权
标题翻译：对准标记与位线之间的水平间隔物，用于对准信号改善
公开(公告)号：US07098546B1
公开(公告)日：2006-08-29
申请号：US10869286
申请日：2004-06-16
申请人： Emmanuil H. Lingunis , Jean Yee-Mei Yang , Hidehiko Shiraiwa
发明人： Emmanuil H. Lingunis , Jean Yee-Mei Yang , Hidehiko Shiraiwa
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L27/115 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L27/11568 , H01L2223/54453 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention pertains to utilizing a salicide in establishing alignment marks in semiconductor fabrication. A metal layer is formed over exposed portions of a silicon substrate as well as oxide areas formed over bitlines buried within the substrate. The metal layer is treated to react with the exposed portions of the silicon substrate to form salicided areas. The metal layer does not, however, react with the oxide areas. As such, salicided areas are formed adjacent to the oxide areas to provide an enhanced optical contrast when light is shined there-upon. In this manner, the alignment marks can be more readily “seen”. The enhanced optical contrast thus allows the marks to continue to be seen as scaling occurs.
摘要翻译：本发明涉及在半导体制造中利用硅化物建立对准标记。在硅衬底的暴露部分上形成金属层，以及形成在衬底内的位线之间形成的氧化物区域。处理金属层与硅衬底的暴露部分反应以形成咸水区域。然而，金属层不与氧化物区域反应。因此，在氧化物区域附近形成有咸水区域，以在其上照射光时提供增强的光学对比度。以这种方式，对准标记可以更容易地“看到”。因此，增强的光学对比度允许标记继续被看作是发生缩放。

18. 发明授权

US06989320B2 Bitline implant utilizing dual poly 有权
标题翻译：利用双重聚合物的位线植入
公开(公告)号：US06989320B2
公开(公告)日：2006-01-24
申请号：US10843289
申请日：2004-05-11
申请人： Weidong Qian , Mark Ramsbey , Jean Yee-Mei Yang , Sameer Haddad
发明人： Weidong Qian , Mark Ramsbey , Jean Yee-Mei Yang , Sameer Haddad
IPC分类号： H01L21/425
CPC分类号： H01L27/115 , H01L27/11568
摘要： The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials are also formed over the buried bitlines to improve (e.g., increase) a breakdown voltage between the bitlines and wordlines, thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process also facilitates a reduction in buried bitline width and thus allows bitlines to be formed closer together. As a result, more devices can be “packed” within the same or a smaller area.
摘要翻译：本发明涉及在形成基于晶体管的存储器件中实现双重聚合工艺。该过程允许以比常规位线更少的能量和更浅的深度形成掩埋位线，以节省资源和空间，并且改善Vt滚降。氧化物材料也形成在掩埋位线上以改善（例如，增加）位线和字线之间的击穿电压，从而允许编程和擦除电荷之间的更大区分，并且更可靠的结果数据存储。该方法还有助于减少掩埋位线宽度，从而允许位线更靠近地形成。因此，更多的设备可以在相同或较小的区域内“打包”。

19. 发明授权

US06744105B1 Memory array having shallow bit line with silicide contact portion and method of formation 有权
标题翻译：具有硅化物接触部分的浅位线的存储器阵列和形成方法
公开(公告)号：US06744105B1
公开(公告)日：2004-06-01
申请号：US10382731
申请日：2003-03-05
申请人： Cinti Xiaohua Chen , Hiroyuki Kinoshita , Jeff P. Erhardt , Weidong Qian , Jean Yee-Mei Yang
发明人： Cinti Xiaohua Chen , Hiroyuki Kinoshita , Jeff P. Erhardt , Weidong Qian , Jean Yee-Mei Yang
IPC分类号： H01L2976
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： A core memory array having a plurality of charge trapping dielectric memory devices. The core memory array can include a substrate having a first semiconductor bit line and a second semiconductor bit line formed therein and a body region interposed between the first and the second bit lines. Over the body region can be formed a first dielectric layer disposed, a dielectric charge trapping layer and a second dielectric layer. At least one word line can be disposed over the second dielectric layer, which defines a channel within the body region. Each bit line can include a bit line contact assembly having a locally metalized portion of the bit line and a conductive via traversing a dielectric region.
摘要翻译：一种具有多个电荷俘获介质存储器件的核心存储器阵列。核心存储器阵列可以包括具有形成在其中的第一半导体位线和第二半导体位线的衬底和插入在第一和第二位线之间的体区。可以在身体区域上形成设置有介电电荷俘获层和第二介电层的第一介电层。至少一条字线可以设置在第二电介质层上，该第二电介质层限定了身体区域内的通道。每个位线可以包括具有位线的局部金属化部分的位线接触组件和穿过电介质区域的导电通孔。

20. 发明授权

US09318333B2 Dielectric extension to mitigate short channel effects 有权
标题翻译：电介质延伸以减轻短路效应
公开(公告)号：US09318333B2
公开(公告)日：2016-04-19
申请号：US11724725
申请日：2007-03-16
申请人： Vidyut Gopal , Shankar Sinha , Jean Yee-Mei Yang , Phillip L. Jones
发明人： Vidyut Gopal , Shankar Sinha , Jean Yee-Mei Yang , Phillip L. Jones
IPC分类号： H01L21/336 , H01L21/28 , H01L21/311 , H01L27/115 , H01L29/66
CPC分类号： H01L21/28123 , H01L21/31144 , H01L27/115 , H01L27/11568 , H01L29/6653
摘要： In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.
摘要翻译：在图案化晶体管时，允许一层栅极电介质材料保留在其上形成晶体管的半导体衬底上。这种剩余的介电材料阻止掺杂剂注入到下面的衬底中，有效地延长晶体管的沟道区。这减轻了诸如泄漏电流等不需要的短通道效应，从而通过建立以更可预测或以其它方式所需的方式执行的晶体管来减轻产量损失。

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