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1. 发明申请

US20080153269A1 Thin oxide dummy tiling as charge protection 有权
标题翻译：薄氧化虚拟平铺作为电荷保护
公开(公告)号：US20080153269A1
公开(公告)日：2008-06-26
申请号：US11645475
申请日：2006-12-26
申请人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
发明人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
IPC分类号： H01L21/20
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11568
摘要： The present invention pertains to a system and method for implementing dummy tiles in forming a memory device. The system and method involves forming at least a portion of a memory core array upon a semiconductor substrate comprising, forming STI structures in the substrate, depositing an oxide layer over the substrate, forming a first polysilicon layer over the oxide layer, doping the first polysilicon layer, forming a second polysilicon layer over the first polysilicon layer, patterning at least one memory core, patterning at least one dummy tile and performing back end processing.
摘要翻译：本发明涉及在形成存储器件时实现虚拟瓦片的系统和方法。该系统和方法包括在半导体衬底上形成存储芯阵列的至少一部分，包括：在衬底中形成STI结构，在衬底上沉积氧化层，在氧化物层上形成第一多晶硅层，掺杂第一多晶硅层，在第一多晶硅层上形成第二多晶硅层，图案化至少一个存储器芯，图案化至少一个虚拟贴片并执行后端处理。

2. 发明授权

US07977218B2 Thin oxide dummy tiling as charge protection 有权
标题翻译：薄氧化虚拟平铺作为电荷保护
公开(公告)号：US07977218B2
公开(公告)日：2011-07-12
申请号：US11645475
申请日：2006-12-26
申请人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
发明人： Cinti Chen , Yi He , Wenmei Li , Zhizheng Liu , Ming-Sang Kwan , Yu Sun , Jean Yee-Mei Yang
IPC分类号： H01L21/00
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11568
摘要： Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.
摘要翻译：新颖的制造方法实现使用虚拟瓦片以避免在形成存储器件区域区域中的在线充电，ESD事件和这种电荷效应的影响。一种方法包括在半导体衬底上形成至少一部分存储器芯阵列，该半导体衬底涉及在衬底中形成基本上围绕阵列内的存储器件区域区域的STI结构。在存储器件区域和STI之上的衬底上形成氧化物层，其中形成在存储器件区域上的氧化物层的内部部分比在STI上形成的氧化物层的外部部分更厚。然后在内部和外部部分上形成第一多晶硅层，包括形成在一个或多个外部部分上并且电连接到至少一个内部部分的一个或多个虚拟瓦片。

3. 发明授权

US07553727B2 Using implanted poly-1 to improve charging protection in dual-poly process 有权
标题翻译：使用植入poly-1改善双重聚合过程中的充电保护
公开(公告)号：US07553727B2
公开(公告)日：2009-06-30
申请号：US11724726
申请日：2007-03-16
申请人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
发明人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
IPC分类号： H01L21/8247
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.
摘要翻译：本发明涉及在形成基于晶体管的存储器件中实现双重聚合工艺。该过程允许在沉积第二多晶硅层之后选择性地掺杂第一多晶硅层。该掺杂增加了第一多晶硅层的导电性，其可以实现针对多位磁芯阵列的更强鲁棒的充电保护和更均匀的电荷分布。

4. 发明申请

US20080150006A1 Using implanted poly-1 to improve charging protection in dual-poly process 有权
标题翻译：使用植入poly-1改善双重聚合过程中的充电保护
公开(公告)号：US20080150006A1
公开(公告)日：2008-06-26
申请号：US11724726
申请日：2007-03-16
申请人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
发明人： Ming-Sang Kwan , Bradley Marc Davis , Jean Yee-Mei Yang , Zhizheng Liu , Yi He
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.
摘要翻译：本发明涉及在形成基于晶体管的存储器件中实现双重聚合工艺。该过程允许在沉积第二多晶硅层之后选择性地掺杂第一多晶硅层。该掺杂增加了第一多晶硅层的导电性，其可以实现针对多位磁芯阵列的更强鲁棒的充电保护和更均匀的电荷分布。

5. 发明申请

US20080153274A1 Deep bitline implant to avoid program disturb 有权
标题翻译：深位线植入，以避免程序干扰
公开(公告)号：US20080153274A1
公开(公告)日：2008-06-26
申请号：US11646157
申请日：2006-12-26
申请人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
发明人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
IPC分类号： H01L21/425 , G11C11/34
CPC分类号： H01L27/11568 , G11C5/02 , G11C5/06 , H01L27/115
摘要： A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.
摘要翻译：一种在半导体衬底上形成双位存储器核心阵列的至少一部分的方法，所述方法包括执行前端处理，执行第一位线注入或袋式注入或二者进入第一位线间隔以建立掩埋的第一位线在衬底内，在电荷俘获电介质和多晶硅层特征之上沉积间隔物材料层，形成与电荷俘获电介质相邻的侧壁隔离层和多晶硅层特征以限定相邻存储器单元之间的第二位线间隔，执行深度砷注入到第二位线间隔中，以在结构内建立比第一位线更深的第二位线，去除侧壁间隔件并执行后端处理。

6. 发明授权

US07671405B2 Deep bitline implant to avoid program disturb 有权
标题翻译：深位线植入，以避免程序干扰
公开(公告)号：US07671405B2
公开(公告)日：2010-03-02
申请号：US11646157
申请日：2006-12-26
申请人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
发明人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
IPC分类号： H01L27/112 , H01L21/336
CPC分类号： H01L27/11568 , G11C5/02 , G11C5/06 , H01L27/115
摘要： A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.
摘要翻译：一种在半导体衬底上形成双位存储器核心阵列的至少一部分的方法，所述方法包括执行前端处理，执行第一位线注入或袋式注入或二者进入第一位线间隔以建立掩埋的第一位线在衬底内，在电荷俘获电介质和多晶硅层特征之上沉积间隔物材料层，形成与电荷俘获电介质相邻的侧壁隔离层和多晶硅层特征以限定相邻存储器单元之间的第二位线间隔，执行深度砷注入到第二位线间隔中，以在结构内建立比第一位线更深的第二位线，去除侧壁间隔件并执行后端处理。

7. 发明授权

US07626869B2 Multi-phase wordline erasing for flash memory 有权
标题翻译：闪存多相字线擦除
公开(公告)号：US07626869B2
公开(公告)日：2009-12-01
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

8. 发明授权

US09171936B2 Barrier region underlying source/drain regions for dual-bit memory devices 有权
标题翻译：用于双位存储器件的源极/漏极区域的屏障区域
公开(公告)号：US09171936B2
公开(公告)日：2015-10-27
申请号：US11634777
申请日：2006-12-06
申请人： Shankar Sinha , Yi He , Zhizheng Liu , Ming-Sang Kwan
发明人： Shankar Sinha , Yi He , Zhizheng Liu , Ming-Sang Kwan
IPC分类号： H01L29/66 , H01L21/265 , H01L27/115 , H01L29/792
CPC分类号： H01L29/66833 , H01L21/26506 , H01L27/115 , H01L27/11568 , H01L29/792
摘要： One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.
摘要翻译：本发明的一个实施例涉及一种存储单元。存储单元包括衬底和布置在衬底上的层叠栅极结构，其中堆叠栅极结构包括适于存储至少一位数据的电荷捕获介电层。存储单元还包括衬底中的源极和漏极，其中源极和漏极设置在堆叠的栅极结构的相对侧。阻挡区域基本上设置在源极或漏极下方并且包括惰性物质。还公开了其他实施例。

9. 发明申请

US20080135902A1 Barrier region for memory devices 有权
标题翻译：存储设备的屏障区域
公开(公告)号：US20080135902A1
公开(公告)日：2008-06-12
申请号：US11634777
申请日：2006-12-06
申请人： Shankar Sinha , Yi He , Zhizheng Liu , Ming-Sang Kwan
发明人： Shankar Sinha , Yi He , Zhizheng Liu , Ming-Sang Kwan
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/66833 , H01L21/26506 , H01L27/115 , H01L27/11568 , H01L29/792
摘要： One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.
摘要翻译：本发明的一个实施例涉及一种存储单元。存储单元包括衬底和布置在衬底上的层叠栅极结构，其中堆叠栅极结构包括适于存储至少一位数据的电荷捕获介电层。存储单元还包括衬底中的源极和漏极，其中源极和漏极设置在堆叠的栅极结构的相对侧。阻挡区域基本上设置在源极或漏极下方并且包括惰性物质。还公开了其他实施例。

10. 发明申请

US20080279014A1 MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY 有权
标题翻译：闪存存储器的多相WORDLINE擦除
公开(公告)号：US20080279014A1
公开(公告)日：2008-11-13
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

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