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    • 11. 发明授权
    • Reconfigurable logic circuit
    • 可重构逻辑电路
    • US07796423B2
    • 2010-09-14
    • US12339638
    • 2008-12-19
    • Hideyuki SugiyamaMizue IshikawaTomoaki InokuchiYoshiaki SaitoTetsufumi Tanamoto
    • Hideyuki SugiyamaMizue IshikawaTomoaki InokuchiYoshiaki SaitoTetsufumi Tanamoto
    • G11C11/00
    • H03K19/1733G11C11/161G11C11/1675G11C11/1697
    • It is made possible to provide a reconfigurable logic circuit with which high integration can be achieved. A reconfigurable logic circuit includes: a multiplexer which includes a plurality of spin MOSFETs each having a source and drain containing a magnetic material, and a selecting portion including a plurality of MOSFETs and selecting a spin MOSFET from the plurality of spin MOSFETs, based on control data transmitted from control lines; a determining circuit which determines whether magnetization of the magnetic material of the source and drain of a selected spin MOSFET, which is selected by the selecting portion, is in a first state or in a second state; and a first and second write circuits which put the magnetization of the magnetic material of the source and drain of the selected spin MOSFET into the second and first states respectively by supplying a write current flowing between the source and drain of the selected spin MOSFET.
    • 可以提供可实现高集成度的可重构逻辑电路。 可重配置逻辑电路包括:多路复用器,其包括多个自旋MOSFET,每个具有包含磁性材料的源极和漏极,以及包括多个MOSFET的选择部分,并且基于控制从多个自旋MOSFET中选择自旋MOSFET 从控制线传输的数据; 确定电路,其确定由选择部分选择的所选择的自旋MOSFET的源极和漏极的磁性材料的磁化是处于第一状态还是处于第二状态; 以及第一和第二写入电路,其通过提供在选定的自旋MOSFET的源极和漏极之间流动的写入电流,将所选自旋MOSFET的源极和漏极的磁性材料的磁化分别置于第二和第一状态。
    • 16. 发明授权
    • Programmable logic circuit
    • 可编程逻辑电路
    • US08294489B2
    • 2012-10-23
    • US12404606
    • 2009-03-16
    • Tetsufumi TanamotoHideyuki SugiyamaKazutaka IkegamiYoshiaki Saito
    • Tetsufumi TanamotoHideyuki SugiyamaKazutaka IkegamiYoshiaki Saito
    • H03K19/177
    • H03K19/1776G11C13/0002H03K19/17764H03K19/1778H03K19/17784H03K19/18
    • A programmable logic circuit includes: an input circuit configured to receive a plurality of input signals; and a programmable cell array including a plurality of unit programmable cells arranged in a matrix form, each of the unit programmable cells including a first memory circuit of resistance change type including a first transistor and a second memory circuit of resistance change type including a second transistor, the first and second memory circuits connected in parallel, each gate of the first transistors on same row respectively receiving one input signal, each gate of the second transistors on same row receiving an inverted signal of the one input signal, output terminals of the first and second memory circuits on same column being connected to a common output line.
    • 可编程逻辑电路包括:输入电路,被配置为接收多个输入信号; 以及包括以矩阵形式布置的多个单元可编程单元的可编程单元阵列,每个单元可编程单元包括电阻改变型的第一存储器电路,包括第一晶体管和包括第二晶体管的电阻变化型的第二存储器电路 并联连接的第一和第二存储器电路,同一行上的第一晶体管的每个栅极分别接收一个输入信号,同一行上的第二晶体管的每个栅极接收一个输入信号的反相信号,第一个输出端的输出端 并且同一列上的第二存储器电路连接到公共输出线。