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1. 发明授权

US07653855B2 Random number test circuit, random number generation circuit, semiconductor integrated circuit, IC card and information terminal device 有权
标题翻译：随机数测试电路，随机数生成电路，半导体集成电路，IC卡和信息终端设备
公开(公告)号：US07653855B2
公开(公告)日：2010-01-26
申请号：US11875360
申请日：2007-10-19
申请人： Shinichi Yasuda , Shinobu Fujita , Koichi Fujisaki , Tetsufumi Tanamoto , Keiko Abe
发明人： Shinichi Yasuda , Shinobu Fujita , Koichi Fujisaki , Tetsufumi Tanamoto , Keiko Abe
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F7/58 , G01R31/3181
摘要： A random number test circuit includes a counting unit to count number of repetitions of a certain-value bit in a random number sequence, the repetitions occurring in series, a detecting unit to detect a plurality of numbers corresponding to a kind of bits in the random number sequence, and a determining unit to determine whether the random number sequence is normal, based on the numbers.
摘要翻译：随机数测试电路包括：计数单元，用于对随机数序列中的特定值比特的重复次数进行计数，串联发生的重复;检测单元，用于检测与随机数中的比特种类对应的多个数字数字序列，以及基于该数字确定随机数序列是否正常的确定单元。

2. 发明申请

US20080046790A1 RANDOM NUMBER TEST CIRCUIT, RANDOM NUMBER GENERATION CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, IC CARD AND INFORMATION TERMINAL DEVICE 有权
标题翻译：随机数测试电路，随机数生成电路，半导体集成电路，IC卡和信息终端设备
公开(公告)号：US20080046790A1
公开(公告)日：2008-02-21
申请号：US11875360
申请日：2007-10-19
申请人： Shinichi Yasuda , Shinobu Fujita , Koichi Fujisaki , Tetsufumi Tanamoto , Keiko Abe
发明人： Shinichi Yasuda , Shinobu Fujita , Koichi Fujisaki , Tetsufumi Tanamoto , Keiko Abe
IPC分类号： G01R31/3183
CPC分类号： G06F7/58 , G01R31/3181
摘要： A random number test circuit includes a counting unit to count number of repetitions of a certain-value bit in a random number sequence, the repetitions occurring in series, a detecting unit to detect a plurality of numbers corresponding to a kind of bits in the random number sequence, and a determining unit to determine whether the random number sequence is normal, based on the numbers.
摘要翻译：随机数测试电路包括：计数单元，用于对随机数序列中的特定值比特的重复次数进行计数，串联发生的重复;检测单元，用于检测与随机数中的比特种类对应的多个数字数字序列，以及基于该数字确定随机数序列是否正常的确定单元。

3. 发明申请

US20050204220A1 Random number test circuit, random number generation circuit, semiconductor integrated circuit, IC card and information terminal device 审中-公开
标题翻译：随机数测试电路，随机数生成电路，半导体集成电路，IC卡和信息终端设备
公开(公告)号：US20050204220A1
公开(公告)日：2005-09-15
申请号：US11067672
申请日：2005-03-01
申请人： Shinichi Yasuda , Shinobu Fujita , Koichi Fujisaki , Tetsufumi Tanamoto , Keiko Abe
发明人： Shinichi Yasuda , Shinobu Fujita , Koichi Fujisaki , Tetsufumi Tanamoto , Keiko Abe
IPC分类号： G06F7/58 , G01R31/28 , G06F11/00 , G09C1/00 , H03K3/84
CPC分类号： G06F7/58 , G01R31/3181
摘要： A random number test circuit includes a counting unit to count number of repetitions of a certain-value bit in a random number sequence, the repetitions occurring in series, a detecting unit to detect a plurality of numbers corresponding to a kind of bits in the random number sequence, and a determining unit to determine whether the random number sequence is normal, based on the numbers.
摘要翻译：随机数测试电路包括：计数单元，用于对随机数序列中的特定值比特的重复次数进行计数，串联发生的重复;检测单元，用于检测与随机数中的比特种类对应的多个数字数字序列，以及基于该数字确定随机数序列是否正常的确定单元。

4. 发明申请

US20130055189A1 METHOD FOR IMPLEMENTING CIRCUIT DESIGN FOR INTEGRATED CIRCUIT AND COMPUTER READABLE MEDIUM 失效
标题翻译：用于集成电路和计算机可读介质实现电路设计的方法
公开(公告)号：US20130055189A1
公开(公告)日：2013-02-28
申请号：US13561483
申请日：2012-07-30
申请人： Kumiko Nomura , Shinichi Yasuda , Shinobu Fujita , Keiko Abe , Tetsufumi Tanamoto , Kazutaka Ikegami , Masato Oda
发明人： Kumiko Nomura , Shinichi Yasuda , Shinobu Fujita , Keiko Abe , Tetsufumi Tanamoto , Kazutaka Ikegami , Masato Oda
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5031 , G06F17/5054 , G06F17/5081
摘要： In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.
摘要翻译：在一个实施例中，一种用于实现集成电路的电路设计的方法包括：（a）获得第一布线以满足给定的工作频率; （b）基于给定的工作频率和第一布线的关键路径计算最大旁路布线长度; （c）通过在第一布线组中使用不同于第一布线的布线的旁路第一布线来获得第二布线，其中集成电路的布线被分类为多个布线组，并且第一布线包括在第一布线中分类布线组的第一接线组; 以及（d）如果所述第二布线和所述第一布线之间的差不大于所述最大旁路布线长度，则用所述第二布线代替所述第一布线，并且如果所述差大于所述最大旁路布线，则不更换所述第一布线长度。

5. 发明授权

US08578318B2 Method for implementing circuit design for integrated circuit and computer readable medium 失效
标题翻译：集成电路和计算机可读介质电路设计实现方法
公开(公告)号：US08578318B2
公开(公告)日：2013-11-05
申请号：US13561483
申请日：2012-07-30
申请人： Kumiko Nomura , Shinichi Yasuda , Shinobu Fujita , Keiko Abe , Tetsufumi Tanamoto , Kazutaka Ikegami , Masato Oda
发明人： Kumiko Nomura , Shinichi Yasuda , Shinobu Fujita , Keiko Abe , Tetsufumi Tanamoto , Kazutaka Ikegami , Masato Oda
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5031 , G06F17/5054 , G06F17/5081
摘要： In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.
摘要翻译：在一个实施例中，一种用于实现集成电路的电路设计的方法包括：（a）获得第一布线以满足给定的工作频率; （b）基于给定的工作频率和第一布线的关键路径计算最大旁路布线长度; （c）通过在第一布线组中使用不同于第一布线的布线的旁路第一布线来获得第二布线，其中集成电路的布线被分类为多个布线组，并且第一布线包括在第一布线中分类布线组的第一接线组; 以及（d）如果所述第二布线和所述第一布线之间的差不大于所述最大旁路布线长度，则用所述第二布线代替所述第一布线，并且如果所述差大于所述最大旁路布线，则不更换所述第一布线长度。

6. 发明授权

US08553464B2 Nonvolatile programmable logic switch 有权
标题翻译：非易失性可编程逻辑开关
公开(公告)号：US08553464B2
公开(公告)日：2013-10-08
申请号：US13240087
申请日：2011-09-22
申请人： Yoshifumi Nishi , Daisuke Hagishima , Shinichi Yasuda , Tetsufumi Tanamoto , Takahiro Kurita , Atsuhiro Kinoshita , Shinobu Fujita
发明人： Yoshifumi Nishi , Daisuke Hagishima , Shinichi Yasuda , Tetsufumi Tanamoto , Takahiro Kurita , Atsuhiro Kinoshita , Shinobu Fujita
IPC分类号： G11C11/35
CPC分类号： H01L27/11568 , G11C16/0458 , G11C16/10 , H01L27/11573 , H01L27/11803
摘要： An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.
摘要翻译：本实施例的一个方面提供了一种非易失性可编程逻辑开关，包括第一存储单元晶体管，第二存储单元晶体管，传输晶体管和向该通过晶体管施加衬底电压的第一衬底电极，其中写入电压为施加到第一布线，第一电压施加到第二布线和第三布线中的一个，并且低于第一电压的第二电压施加到第二布线和第三布线中的另一布线，第一基板当数据被写入第一存储单元晶体管或第二存储单元晶体管时，高于第二电压并低于第一电压的电压被施加到传输晶体管的阱。

7. 发明申请

US20080244489A1 METHOD AND APPARATUS FOR DESIGNING A THREE-DIMENSIONAL INTEGRATED CIRCUIT 有权
标题翻译：用于设计三维集成电路的方法和装置
公开(公告)号：US20080244489A1
公开(公告)日：2008-10-02
申请号：US12047547
申请日：2008-03-13
申请人： Tetsufumi Tanamoto , Shinichi Yasuda , Shinobu Fujita
发明人： Tetsufumi Tanamoto , Shinichi Yasuda , Shinobu Fujita
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method of designing a three-dimensional integrated circuit includes dividing two-dimensional layout data of a circuit formed on a semiconductor substrate into a plurality of layout block data in order to re-arrange in different layers, generating layout block data reversing one of the layout block data of two folded layers arranged vertically adjacent to each other, alternately arranging the reversed layout block data and non-reverse block layout data to form a plurality of layers vertically overlapped, selecting at least one from interconnects included in a plurality of layout block data of the circuit and ranging over plural layers so as to be mutually and functionally collected together with respect to at least one of time delay, interconnect length and block configuration, and re-arranging the selected interconnect using a via connecting an upper layer and an under layer of the folded interconnect.
摘要翻译：一种设计三维集成电路的方法包括将形成在半导体衬底上的电路的二维布局数据划分成多个布局块数据，以便重新排列在不同的层中，生成布局块数据，交替布置反向布局块数据和非反向块布局数据以形成垂直重叠的多个层的两个折叠层的布局块数据，从包括在多个布局块中的互连中选择至少一个层电路的数据并且跨越多个层，以便相对于时间延迟，互连长度和块配置中的至少一个而相互和功能地收集在一起，并且使用连接上层和第二层的通孔重新布置所选择的互连折叠互连的下层。

8. 发明授权

US07949984B2 Method and apparatus for designing a three-dimensional integrated circuit 有权
标题翻译：用于设计三维集成电路的方法和装置
公开(公告)号：US07949984B2
公开(公告)日：2011-05-24
申请号：US12047547
申请日：2008-03-13
申请人： Tetsufumi Tanamoto , Shinichi Yasuda , Shinobu Fujita
发明人： Tetsufumi Tanamoto , Shinichi Yasuda , Shinobu Fujita
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method of designing a three-dimensional integrated circuit includes dividing two-dimensional layout data of a circuit formed on a semiconductor substrate into a plurality of layout block data in order to re-arrange in different layers, generating layout block data reversing one of the layout block data of two folded layers arranged vertically adjacent to each other, alternately arranging the reversed layout block data and non-reverse block layout data to form a plurality of layers vertically overlapped, selecting at least one from interconnects included in a plurality of layout block data of the circuit and ranging over plural layers so as to be mutually and functionally collected together with respect to at least one of time delay, interconnect length and block configuration, and re-arranging the selected interconnect using a via connecting an upper layer and an under layer of the folded interconnect.
摘要翻译：一种设计三维集成电路的方法包括将形成在半导体衬底上的电路的二维布局数据划分成多个布局块数据，以便重新排列在不同的层中，生成布局块数据，交替布置反向布局块数据和非反向块布局数据以形成垂直重叠的多个层的两个折叠层的布局块数据，从包括在多个布局块中的互连中选择至少一个层电路的数据并且跨越多个层，以便相对于时间延迟，互连长度和块配置中的至少一个而相互和功能地收集在一起，并且使用连接上层和第二层的通孔重新布置所选择的互连折叠互连的下层。

9. 发明授权

US08742810B2 PLL (phase-locked loop) 失效
标题翻译： PLL（锁相环）
公开(公告)号：US08742810B2
公开(公告)日：2014-06-03
申请号：US13461101
申请日：2012-05-01
申请人： Hiroki Noguchi , Keiko Abe , Shinichi Yasuda , Shinobu Fujita
发明人： Hiroki Noguchi , Keiko Abe , Shinichi Yasuda , Shinobu Fujita
IPC分类号： H03L7/06
CPC分类号： H03L7/14 , H03L2207/18
摘要： One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value.
摘要翻译：一个实施例提供了一种锁相环（PLL），其中定序器控制环路滤波器，使得当指示关闭PLL的电源的信号被输入时，或者当指示接通 PLL的电源被输入到其中，环路滤波器中的第一电阻改变装置的电阻值是第一电阻值，并且在PLL稳定之后，第一电阻改变装置的电阻值是第二电阻值电阻值高于第一电阻值。

10. 发明授权

US08497732B2 Three-dimensional semiconductor integrated circuit 有权
标题翻译：三维半导体集成电路
公开(公告)号：US08497732B2
公开(公告)日：2013-07-30
申请号：US13223898
申请日：2011-09-01
申请人： Shinichi Yasuda , Keiko Abe , Shinobu Fujita
发明人： Shinichi Yasuda , Keiko Abe , Shinobu Fujita
IPC分类号： H01L25/00
CPC分类号： H03K19/20 , G11C5/02 , H01L23/642 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/18 , H01L2224/48091 , H01L2224/49113 , H01L2225/06513 , H01L2225/06527 , H01L2225/06531 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01033 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19104 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： According to one embodiment, a three-dimensional semiconductor integrated circuit includes first, second and third chips which are stacked, and a common conductor which connects the first, second and third chips from one another. The first chip includes a first multi-leveling circuit, the second chip includes a second multi-leveling circuit, and the third chip includes a decoding circuit. The first multi-leveling circuit includes a first inverter to which binary first data is input and which outputs one of first and second potentials and a first capacitor which is connected between an output terminal of the first inverter and the common conductor. The second multi-leveling circuit includes a second inverter to which binary second data is input and which outputs one of third and fourth potentials and a second capacitor which is connected between an output terminal of the second inverter and the common conductor.
摘要翻译：根据一个实施例，三维半导体集成电路包括堆叠的第一，第二和第三芯片，以及将第一，第二和第三芯片彼此连接的公共导体。第一芯片包括第一多电平电路，第二芯片包括第二多电平电路，第三芯片包括解码电路。第一多电平电路包括输入二进制第一数据并输出第一和第二电位之一的第一反相器和连接在第一反相器的输出端和公共导体之间的第一电容器。第二多电平电路包括输入二进制第二数据并输出第三和第四电位之一的第二反相器和连接在第二反相器的输出端和公共导体之间的第二电容器。

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