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11. 发明专利

JPS61152039A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61152039A
公开(公告)日：1986-07-10
申请号：JP27309584
申请日：1984-12-26
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： NAKAGAWA TAKASHI , KOYAMA YOSHIHISA
IPC分类号： H01L21/3213 , H01L21/88
摘要： PURPOSE:To perform microscopic processing on a metal film without using a multilayer resist structure and to obtain a high-accuracy wiring and a semiconductor device with fuse by a method wherein the oxide coated film on the surface of the metal film is colored, a photo absorption layer consisting of the colored layer of the oxide coated film is provided on the surface of the metal film and the reflectivity of the metal film is made to reduce. CONSTITUTION:An oxide coated film of several tens Angstrom or thereabouts is provided on the surface of an Al evaporated film 3. This oxide coated film is generally a gamma-al2O3 film, is porous from the mechanism of its formation, is rich in absorption and is easy to dye. The oxide coated film, which is the surface layer of the Al evaporated film 3, is colored and a photo absorption layer 4 consisting of the colored layer is provided. Then, a photo resist film 5 is formed. A pattern exposure is performed turning the photo resist film 5 to the wiring pattern. At the time of this exposure, as the photo absorption layer 4 is being provided on the surface of the Al evaporated film 3 having a high reflectivity, the light of a photosensitive wavelength is absorbed in the colored layer of the photo absorption layer 4, and the reflection of light from the steps and the adjacent patterns and the reflection of light from the surface of the Al evaporated film 3, which is the base, can be exposure reaches so deep as to deep as to the light-shielding part consisting of a mask, there is no need to use a multilayer resist structure in a microscopic processing technique according to photolithography.

12. 发明专利

JPS60242586A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60242586A
公开(公告)日：1985-12-02
申请号：JP9654684
申请日：1984-05-16
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KITAME TETSUYA , KOYAMA YOSHIHISA , SAKAI KIKUO , OGATA SHINKOU , YOSHIDA MASAHIRO
IPC分类号： G11C11/407 , G11C11/34
摘要： PURPOSE:To discriminate variation in source voltage precisely and prevent malfunction by dividing the source voltage through conduction type MOSFETs which are supplied with the source voltage as a bias voltage. CONSTITUTION:The source voltage is divided through series-connected P type FETs Q45 and Q46 which are supplied with the source voltage VCC as a bias voltage and compared by an inverter IV2 with a reference voltage, thereby discriminating variation in the source voltage. Therefore, the semiconductor substrate of single-crystal P type silicon of the integrated circuit of an internal synchronism type dynamic RAM formed on the substrate is not affected by the bias voltage developed in the substrate, and a desired divided voltage of the source voltage is obtained to detect variation in the source voltage accurately, so that the variation in the source voltage is discriminated with high precision. Consequently, a proper timing signal is generated even when the source voltage varies, and the semiconductor integrated circuit of the dynamic RAM is prevented from malfunctioning.

13. 发明专利

JPS6021554A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6021554A
公开(公告)日：1985-02-02
申请号：JP12770983
申请日：1983-07-15
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KOYAMA YOSHIHISA , MIYAZAWA HIROYUKI
IPC分类号： H01L27/04 , H01L21/768 , H01L21/822 , H01L23/522 , H01L23/62 , H01L29/78
摘要： PURPOSE:To prevent current breakdown by a method wherein the width of contact of the first semiconductor layer with the second semiconductor layer is formed larger than that of either one semiconductor layer of the first and second ones. CONSTITUTION:The rectangular region of the second semiconductor layer 14 formed under a contact hole 11 is formed by extension from under a polycrystalline Si layer 8 toward the first conductive layer 13. The width W2 of a region 15 etched at the time of etching the polycrystalline Si layer on the second semiconductor layer 14 is formed sufficiently larger than W1. This increase of area causes the decrease of resistance of the region 14 and has the strong property to current breakdown. Therefore, this device is endurable to the current breakdown when an over current is inputted.

14. 发明专利

JPS59229786A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS59229786A
公开(公告)日：1984-12-24
申请号：JP10268783
申请日：1983-06-10
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： YOSHIDA MASAHIRO , KEMIZAKI KANEHIDE , MATSUURA NOBUKI , KOYAMA YOSHIHISA , OGATA SHINKOU
IPC分类号： G11C11/41 , G11C11/34 , G11C11/403
摘要： PURPOSE:To prevent a malfunction of a timing control circuit which is due to the noise produced from an electric power supply line by making use of the action timing signal of a data output buffer to make a edge trigger circuit blind when the actuation is started. CONSTITUTION:An edge detection signal phi is supplied to a timing control circuit TG with variation of an address signal to produce a series of required timing signals. Plural data output buffers are started all at once when a timing signal phiop which starts a data output buffer has the rise in a reading mode. In this case, an edge trigger circuit EG is made blind with a timing signal phidk produced from an AND circuit which receives the signal phiop and a delay signal phiop' of the inverse signal of the signal phiop. Therefore the signal phi is never transmitted to the circuit TG in such a case where a malfunction is produced by the noise of a power supply line due to a fact that plural data output buffers are started all at once.

15. 发明专利

JPH056964A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH056964A
公开(公告)日：1993-01-14
申请号：JP29508991
申请日：1991-10-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KOYAMA YOSHIHISA , SUZUKI YUKIE , MURANAKA MASAYA , MATSUURA NOBUMI , II HARUO , YOSHIKAWA KAZUE , ABE JUNICHI , ARAI KOJI
IPC分类号： H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/08 , H01L27/10 , H01L27/108
摘要： PURPOSE:To prevent a latch-up of approaching circuit elements by providing a guard region coupled to a bonding pad for absorbing a substrate current between a junction region and an active element region formed with an internal circuit. CONSTITUTION:A guard region G5 made of a diffused layer and/or a well region to be coupled to a power source voltage of a circuit of a ground potential, is provided between a junction region disposed near a corresponding bonding pad PAD for constituting an electrostatic protective circuit GC and data output buffer, etc., for a dynamic RAM, etc., and an active element region ACT formed with an internal circuit. Since a breakdown current, a forward current flowing through the junction region can be absorbed through the region G5, a variation in a substrate potential due to the currents can be suppressed. Thus, a latch-up of near circuit elements of the region ACT can be prevented.

16. 发明专利

JPH04155689A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04155689A
公开(公告)日：1992-05-28
申请号：JP27960790
申请日：1990-10-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KOYAMA YOSHIHISA , SUZUKI YUKIE
IPC分类号： G11C11/409 , G11C11/401 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To improve electrostatic breakdown voltage of a short MOSFET by providing clamp MOSFETs between first, second common source lines and a low level power terminal. CONSTITUTION:Clamp MOSFETs Q24 coupled at gate and source electrodes to a low level power terminal VSS are respectively provided at common source lines CSL1, CSL2. If the level of a common source line is set lower by a threshold value voltage or more of the Q24 than a power source voltage VSS, the FET Q24 is turned ON to tend to lift the level of the common source line. When the level of the common source line is considerably higher than a high level side power source voltage, the level of the source line is lowered by the FET Q24. Even if a high voltage is applied by the FET Q24, it is released to other pin to prevent the abnormal voltage rise of an FET Q20.

17. 发明专利

JPS61217992A DYNAMIC TYPE RAM 失效
公开(公告)号：JPS61217992A
公开(公告)日：1986-09-27
申请号：JP5840585
申请日：1985-03-25
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： KOYAMA YOSHIHISA
IPC分类号： G11C11/409 , G11C11/34 , G11C11/401
摘要： PURPOSE:To stabilize an operation by continuously supplying a half precharge level to the complementary data line of the memory array of one non-selected side by a level conpensating circuit even when, a continuous access like a static column mode or a page mode is carried out to the other memory array. CONSTITUTION:The data line of a memory array MARY-L, MARY-R in which a word line is not selected is brought into a floating condition, thereby, in order to prevent is precharge level from level changing by a coupling or a leak current, a level compensating circuit is provided. Namely, to complementary data lines D, inverse of D of a left side memory array MARY-L, a dividing voltage of Vcc/2 formed by potential dividing resistances R1, R2 is supplied through transmitting gates MOSFET Q1-Q4 controlled by a timing signal of inverse of phiL. Also in the right side memory array MARY-R, a similar level compensating circuit is provided.

18. 发明专利

JPS61104396A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS61104396A
公开(公告)日：1986-05-22
申请号：JP22219084
申请日：1984-10-24
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KOYAMA YOSHIHISA
IPC分类号： G11C11/401 , G11C11/34
摘要： PURPOSE: To reduce a rush current of the time when a power source is turned on, by controlling an FET between an inverter of a timing circuit and the ground by an FET coupled with a power source by the same conductive type.
CONSTITUTION: "The gate potential of P type FETs Q2WQ5 for connecting an input of inverters IV2, IV4...IV8 and the ground, in CMOS inverters IV1WIV5 for generating a preamplifier timing signal ϕP
a and an inversion ϕP
a , when a power source is turned on is turned on by L of a floating state by a parasitic input capacity. Accordingly, the input of the inverters IV2, IV4...IV8 becomes a ground potential and the output becomes H, and as for an input level of the invertors IV1WIV8, a period in which it becomes an intermediate level is shortened. When the power supply voltage exceeds a threshold level, a P type FETQ1 whose gate is connected to the ground is turned on, the gate is controlled and the FETs Q2WQ5 are turned off. According to such constitution as a period in which an input of the inverter becomes an intermediate level, when the power source is turned on, a through-current is suppressed, and a rush current of the time when the power source is turned on is reduced.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了减少电源接通时的冲击电流，通过使用相同导电类型的与电源耦合的FET来控制定时电路的反相器与地之间的FET。构成：在用于产生前置放大器定时信号phiPa和反相phiPa的CMOS反相器IV1-IV5中用于连接反相器IV2，IV4 ... IV8和地的输入端的P型FET Q2-Q5的栅极电位，当电源通过寄生输入容量导通浮动状态L。因此，反相器IV2，IV4 ... IV8的输入成为接地电位，输出变为H，对于反相器IV1〜IV8的输入电平，缩短了变为中间电平的期间。当电源电压超过阈值电平时，栅极连接到地的P型FETQ1导通，栅极被控制，FET Q2-Q5截止。根据逆变器的输入为中间电平的期间的结构，当电源接通时，抑制通电，并且电源接通时的冲击电流减少。

19. 发明专利

JPS59117795A Discriminating circuit in semiconductor integrated circuit 失效
标题翻译：在半导体集成电路中识别电路
公开(公告)号：JPS59117795A
公开(公告)日：1984-07-07
申请号：JP22630582
申请日：1982-12-24
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KOYAMA YOSHIHISA
IPC分类号： G11C11/413 , G06F11/00 , G11C29/00 , G11C29/04
CPC分类号： G06F11/006
摘要： PURPOSE:To discriminate easily and surely a failed part after the package assembling of a memory provided with a redundancy circuit by connecting a fuse of a programmable element and a transistor (TR) of diode operation and impressing a reverse potential to the connection. CONSTITUTION:No current is conducted to the FETQ3, Q4 of diode connection connected to the fuse 4 of a discriminating circuit 3 at the normal operation when voltages at terminals VCC, VSS are at power supply voltage and ground voltage respectively, and no effect on an output buffer circuit is given because of the connection of the circuit 3. In impressing the reverse potential to the terminals VCC and VSS, when the fuse 4 is not blown, a node N1' reaches a prescribed voltage dividing potential by the FETQ3, Q4, and when the fuse is blown, the potential reaches a high potential depending on the FETQ4. When the potential depending on the discrimination of the presence of a failure via the bonding and section 2 is observed, the discrimination of a failed part is attained easily and surely even after the package assembling.
摘要翻译：目的：通过连接可编程元件的熔丝和二极管操作的晶体管（TR），并向连接施加反向电位，在设有冗余电路的存储器的封装组装之后，容易且可靠地区分故障部分。构成：在VCC，VSS端子的电压分别为电源电压和接地电压时，二极管连接的FETQ3，Q4在正常工作时连接到鉴别电路3的保险丝4，没有电流由于电路3的连接，给出了输出缓冲电路。在给端子VCC和VSS施加反向电位时，当熔丝4不熔断时，节点N1'通过FETQ3，Q4达到规定的分压电位，当保险丝熔断时，根据FETQ4，电位达到高电位。当观察到根据通过接合和部分2鉴别故障的电位时，即使在封装组装之后也能容易且可靠地实现对故障部件的识别。

20. 发明专利

JPH04349294A DYNAMIC TYPE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04349294A
公开(公告)日：1992-12-03
申请号：JP12339791
申请日：1991-05-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KOYAMA YOSHIHISA , SUZUKI YUKIE
IPC分类号： G11C11/404 , G11C11/407
摘要： PURPOSE:To prevent an insulating film under a plate electrode from being collapsed with static electricity by interposing a switch for power supply/ interruption between an external source voltage terminal or a Vcc/2 generator and the plate electrode. CONSTITUTION:This memory is constituted so that the Vcc/2 voltage generated in the Vcc/2 generator 5 is capable to supply to the plate electrode in a memory array through a switch MOSQ1 and to a data line and to a sense amplifier through a switch MOSQ2. In such a case, when a start detecting signal WK is supplied to a Vcc/2 supply control signal generator 6, a supply control signal VPLC to be its output signal is low level, thus, switches MOSQ1, Q2 are turned off and even when the Vcc/2 voltage is generated in the Vcc/2 generator, the supply is interrupted. On the contrary, when high voltage as static electricity is impressed transiently to the source voltage terminal, since switchs MOSQ1, Q2 are turned off, high voltage is unsupplied to the plate electrode and the collaps of the insulating film is prevented.

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