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1. 发明专利

JPS6013400A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6013400A
公开(公告)日：1985-01-23
申请号：JP11834483
申请日：1983-07-01
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KOYAMA YOSHIHISA
IPC分类号： G11C29/00 , G11C29/42 , G11C29/44
摘要： PURPOSE:To execute rational operation in accordance with the existance of a defective bit and application by controlling a switching gate circuit in accordance with the existence of the fusion of a fuse means. CONSTITUTION:The fuse means F is formed by an aluminum layer. Namely, an extremely thin wire is connected between pads P1 and P2 formed by the aluminum layers to play a roll as a fuse. The quality of the semiconductor storage device is discriminated and tested in a wafer providing process when the semiconductor storage device is completed on a semiconductor wafer. If high speed operation/low power consumption is necessary for the semiconductor storage device discriminated to have resultant high quality, said fuse means F is held as it is without fusion. Thus, power supply voltage is supplied to the input of an inverter IV1 through the fuse means F, so that the output signal of the inverter IV1 is turned to a low level (logical ''0'') and AND gate such as gates G2, G5 receiving a signal from an ECC circuit are closed.

2. 发明专利

JPS60161658A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60161658A
公开(公告)日：1985-08-23
申请号：JP1523584
申请日：1984-02-01
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KOYAMA YOSHIHISA
IPC分类号： H01L27/08 , H01L27/092 , H01L29/78
摘要： PURPOSE:To enhance reliability and yield of a semiconductor integrated circuit device by a method wherein an MISFET for checking of latch locking having short channel length and high transconductance is provided to the part being apt to generate the rise of electric potential of a semiconductor substrate. CONSTITUTION:An MISFET for checking of latch locking (a p-channel MISFET) QA is constructed of a gate electrode 5, an insulating film 4, a semiconductor substrate 1 and a semiconductor region 7C to be used as a source region or a drain region, and a semiconductor region 6C to be formed with the channel region thereof. Because channel length Lg thereof can be controlled according to the diffusion speed of impurities for formation of the semiconductor regions 6C, 7C, channel length can be formed extremely short, and high transconductance (gm) can be obtained. When an external noise voltage to exceed earth potential VSS is generated, the MISFET for checking of latch locking QA is made to be in the ''ON'' condition to remove the external noise voltage of the earth potential VSS or more. Accordingly, a latch locking phenomenon can be checked.

3. 发明专利

JPS6013395A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6013395A
公开(公告)日：1985-01-23
申请号：JP11834283
申请日：1983-07-01
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KOYAMA YOSHIHISA
IPC分类号： G11C11/407 , G11C11/34
摘要： PURPOSE:To prevent the floating of a non-selecting word line due to the coupling between a word line without increasing the number of element by arranging the word line selected by output signal of adjacent address recorder circuit alternately. CONSTITUTION:MOSFETs Q19-22 and Q39-42 for preventing the floating of the word line at a non-selecting time are connected between respective word lines WL1-4 and WL5-8 and the earth potential of the circuit. When one word line coupled with the same output such as an address decoder part NOR1 (or 2) is selected by word line selecting timing signals phix00-11, word lines to which earth potential is applied by the non-selecting signal of the adjacent address decoder part NOR 2 (or 1) are alternately arranged to prevent the floating of the adjacent non-selecting word lines out of three remaining word lines. Namely, the word lines coupled with the adjacent address decoder parts like WL1, WL5, WL2, WL6,... are alternately arranged.

4. 发明专利

JPS6013394A MOS STORAGE MEMORY 失效
公开(公告)号：JPS6013394A
公开(公告)日：1985-01-23
申请号：JP11834183
申请日：1983-07-01
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KOYAMA YOSHIHISA
IPC分类号： G11C11/409 , G11C11/34
摘要： PURPOSE:To prevent the influence of the parasitic capacity of a power supply line to exert upon the precharging operation of complementary data lines by short circuiting also a pair of common power supply lines in the precharging period to turn off an MOSFET constituting a sense amplifier. CONSTITUTION:Power supply voltage Vcc is supplied to a latch circuit through p channel MOSFETs Q12, Q13 which are connected in parallel and the earth voltage Vss of the circuit is supplied through n channel MOSFETs Q10, Q11 connected in parallel. These power switches MOSFET Q10, Q11 and Q12, Q13 are used in common for sense amplifiers arranged in other similar lines. A reset MOSFET Q45 to be turned on in the precharging period is connected between a pair of power supply lines N1, N2 having said constitution. The potential between complementary data lines is increased by the amplification of SA and then the MOSFETs Q11, Q13 having comparative conductance are turned on to speed up the amplification.

5. 发明专利

JPS58166827A DELAY CIRCUIT 失效
公开(公告)号：JPS58166827A
公开(公告)日：1983-10-03
申请号：JP4888782
申请日：1982-03-29
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SATOU KATSUYUKI , KOYAMA YOSHIHISA
IPC分类号： H03K5/13
摘要： PURPOSE:To extend the delay time for a delay circuit having a large time constant, by avoiding the effect of variation of the power supply voltage to the delay time although an input signal has dependance on the power supply voltage. CONSTITUTION:Load MOSFETs Q5 and Q6 are connected in series between MOSFETs Q2 and Q4 which are driven by two signals phi1 and phip' having almost opposite phases to each other. Then the gate voltage which is a little higher than the threshold voltage is supplied to a driving MOSFETQd. This process can eliminate the dependance on the power supply voltage for the delay time. Then the stable delay time is obtained even at the side of high voltage.

6. 发明专利

JPS60242587A DYNAMIC RAM 失效
公开(公告)号：JPS60242587A
公开(公告)日：1985-12-02
申请号：JP9654784
申请日：1984-05-16
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： YOSHIDA MASAHIRO , SAKAI KIKUO , KOYAMA YOSHIHISA , KITAME TETSUYA , OGATA SHINKOU
IPC分类号： G11C11/403 , G11C11/34 , G11C11/401 , G11C29/00 , G11C29/14 , G11C29/50
摘要： PURPOSE:To perform automatic starting operation and test lower-limit voltage operation selectively when the power source is turned on by stopping the operation of the dummy cycle starting circuit of an automatic starting circuit forcibly with a signal from an external terminal. CONSTITUTION:When the chip select signal CS' from the external terminal goes up to a level higher than H which is used normally, an MOSFET47 with a high threshold value is turned on. Then an H output is impressed to close a NAND gate G, the transmission of timing pulses phi' for starting from the dummy cycle starting circuit of the automatic starting circuit consisting of the voltage dividing circuit composed of P channel MOSFETs Q45 and Q46, an inverter IV2, a delay circuit DL, etc., is inhibited, and a source voltage VCC is lowered to test the lower-limit voltage operation, etc. Consequently, the dynamic RAM performs the automatic starting operation and lower-limit voltage operation testing selectively when powered on.

7. 发明专利

JPS60109249A MULTILAYER INTERCONNECTION MEMBER 失效
公开(公告)号：JPS60109249A
公开(公告)日：1985-06-14
申请号：JP21631383
申请日：1983-11-18
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KOYAMA YOSHIHISA
IPC分类号： H01L27/10 , H01L21/3205 , H01L21/8242 , H01L23/52 , H01L27/04 , H01L27/108
摘要： PURPOSE:To contrive to improve the operating speed of the information write and readout of a DRAM by reduction in the resistance value of word lines by a method wherein a word line extending in a fixed direction and a stepwise difference present in the MISFET-forming region of a memory cell are put into intersection at a required angle. CONSTITUTION:The MISFET-forming region of the memory cell is provided in the state that a conductive plate 6 is opened so as to expose that section. Thereby, the stepwise difference S having a steep form is present on insulation films 7 and 8 at part of word line formation and on a field insulation film 4 by means of the insulation film 4, conductive plate, etc. The word line 9 is constructed by coating a polycrystalline Si layer 9A with a silicide layer 9B, the compound of a high melting point metal of a lower resistance and silicon. Since the word line and the stepwise difference are in intersection at a required angle, a current route that avoids a higher resistance part than the flat part generating at the stepwise difference, i.e., a current route that does not orthogonally intersect with the end of said stepwise difference, can be provided, and the resistance value of the word line can be reduced.

8. 发明专利

JPH0572754B2 失效
公开(公告)号：JPH0572754B2
公开(公告)日：1993-10-12
申请号：JP21631383
申请日：1983-11-18
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KOYAMA YOSHIHISA
IPC分类号： H01L27/10 , H01L21/3205 , H01L21/8242 , H01L23/52 , H01L27/04 , H01L27/108 , H01L21/90

9. 发明专利

JPS61194867A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61194867A
公开(公告)日：1986-08-29
申请号：JP3439185
申请日：1985-02-25
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KOYAMA YOSHIHISA
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/78
摘要： PURPOSE:To suppress the fluctuation of the ratio of the capacity value between the capacitive elements due to the dispersion in processing by a method wherein a capacitive elements having different capacity value of prescribed ratio by means of an insulating film consisting of different crystalline faces in the case of an integrated circuit device having capacitive elements with small holes. CONSTITUTION:A field insulation film 2 electrically separates semiconductor elements and limits the formation-region for them in a semiconductor substrate 1. A small hole 3A is provided on the main plane on the memory cell-formation region of the semiconductor substrate 1, and all the side planes consist of (100) crystalline planes. A small hole 3C is provided on the main plane on the dummy cell-formation region of the semiconductor substrate 1, and all the side planes consist of (100) crystalline faces. Insulation films 4A and 4C are provided on the main upper plane of the semiconductor substrate 1 along the small holes 3A and 3C. The insulation film 4A constitutes a capacitive element for storing information, and the insulation film 4C constitutes a capacitive element for judging information.

10. 发明专利

JPS61166064A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS61166064A
公开(公告)日：1986-07-26
申请号：JP19962384
申请日：1984-09-26
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KOYAMA YOSHIHISA
IPC分类号： H01L27/10 , H01L21/82 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To capture unnecessary minority carries intruding to a depletion layer constituting a small hole type capacitance element sufficiently by constituting a carrier capture region by using a small hole or a small groove formed extended in the internal direction of a substrate from the main surface of the substrate. CONSTITUTION:Etching masks in the upper sections of a main surface, to which small holes 13 and 19 are shaped, of a substrate 1 are removed selectively, and the small holes 13 and 19 are formed by employing an anisotropic etching technique. The etching masks used for shaping the small holes 13 and 19 are removed, and insulating films 14 and 20 coating the inner walls of the small holes and the main surface of the substrate 1 are formed. Conductive layers 15 and 21 are formed. A conductive layer 22 and an insulating film 26 are shaped. The conductive layer 22 is formed by employing a polycrystalline silicon layer through a CVD technique. The polycrystalline silicon layer is connected electrically to the conductive layers 15 and 19, and shaped to the upper sections of a field insulating film 9 and the insulating films 14, 20, and an impurity is introduced. The polycrystalline silicon layers in the upper sections of regions, in which a MISFET and a semiconductor region 23 are formed, of the substrate 1 are removed selectively.

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