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1. 发明专利

JPS60242585A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS60242585A
公开(公告)日：1985-12-02
申请号：JP9654084
申请日：1984-05-16
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： MATSUURA NOBUKI , KAJIMOTO TAKESHI , MIYAZAWA KAZUYUKI
IPC分类号： G11C11/409 , G11C11/34
摘要： PURPOSE:To increase the readout speed and optimize the sense margin by connecting a capacitive element to the common source line of a sense amplifier and setting a couple of data lines to a desired precharge level. CONSTITUTION:An MOS capacitor Cmp or Cmn utilizing the gate of an MOS FET is connected selectively to one of common source lines CSp and CSm of the sense amplifier SA equipped with MOSFETs Q5 and Q6 for controlling connections with a high and a low power source. This connection of the capacitor sets precharge levels of a couple of data lines D and D' to a desired value, and the precharge levels are not set to a half as high as a source voltage VCC, but adjusted to the optimum level according to data lines at sides L and H; and the rising of the data lines is speeded up, the readout speed is increased, and the sense margin is optimized.

2. 发明专利

JPS59229786A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS59229786A
公开(公告)日：1984-12-24
申请号：JP10268783
申请日：1983-06-10
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： YOSHIDA MASAHIRO , KEMIZAKI KANEHIDE , MATSUURA NOBUKI , KOYAMA YOSHIHISA , OGATA SHINKOU
IPC分类号： G11C11/41 , G11C11/34 , G11C11/403
摘要： PURPOSE:To prevent a malfunction of a timing control circuit which is due to the noise produced from an electric power supply line by making use of the action timing signal of a data output buffer to make a edge trigger circuit blind when the actuation is started. CONSTITUTION:An edge detection signal phi is supplied to a timing control circuit TG with variation of an address signal to produce a series of required timing signals. Plural data output buffers are started all at once when a timing signal phiop which starts a data output buffer has the rise in a reading mode. In this case, an edge trigger circuit EG is made blind with a timing signal phidk produced from an AND circuit which receives the signal phiop and a delay signal phiop' of the inverse signal of the signal phiop. Therefore the signal phi is never transmitted to the circuit TG in such a case where a malfunction is produced by the noise of a power supply line due to a fact that plural data output buffers are started all at once.

3. 发明专利

JPS59210591A Dynamic memory 失效
标题翻译：动态记忆
公开(公告)号：JPS59210591A
公开(公告)日：1984-11-29
申请号：JP8274783
申请日：1983-05-13
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KEMIZAKI KANEHIDE , MIYAZAWA KAZUYUKI , MATSUURA NOBUKI
IPC分类号： G11C11/409 , G11C11/34 , G11C11/401
CPC分类号： G11C11/34
摘要： PURPOSE:To facilitate test and appraisal and simplify initializing by providing a change-over circuit in input/output route of signal of a pair of complementary data lines and changing common data lines of true system and bar system automatically responding to proper address signal. CONSTITUTION:An intermediate change-over circuit 7 of common data lines CD, -CD consists of MOSFETQ11-Q14, and is on/off controlled receiving internal address signals ax1, -ax1 from an address buffer circuit 2 to the gate. A memory array 1 and an X decoder circuit 3 are so constituted that when internal address signal ax1 is high level, memory cell of D side of data line is selected, and when the signal -ax1 is high level, memory cell of -D side of data line is selected. Accordingly, reading and writing of memory cell of -D side of data line are made entirely in similar way with that of memory cell of D side of data line.
摘要翻译：目的：通过在一对互补数据线的信号的输入/输出路径中提供转换电路并改变真实系统和条形系统的公共数据线，自动响应正确的地址信号，便于测试和评估并简化初始化。构成：公共数据线CD，-CD的中间转换电路7由MOSFETQ11-Q14组成，并且被接通/断开控制，从地址缓冲电路2接收到内部地址信号ax1，-ax1到门。存储器阵列1和X解码器电路3被构造成当内部地址信号ax1为高电平时，选择数据线的D侧的存储单元，并且当信号-ax1为高电平时，-D侧的存储单元的数据线被选中。因此，数据线的-D侧的存储单元的读取和写入完全与数据线的D侧的存储单元的读取和写入完全相同。

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