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11. 发明专利

JPS60163280A MODULATING SYSTEM OF DIGITAL SIGNAL 失效
公开(公告)号：JPS60163280A
公开(公告)日：1985-08-26
申请号：JP1522784
申请日：1984-02-01
申请人： HITACHI LTD , HITACHI ELECTRONICS , HITACHI VIDEO ENG
发明人： ROKUTA MORIHITO , MITA SEIICHI , IZUMIDA MORIJI , KANEDA HIDEHIRO , SHIONO HIROSHI
IPC分类号： H03M5/06 , G11B20/14 , G11B20/16 , H03M7/14 , H04L25/49
摘要： PURPOSE:To reduce a clock rate less than a 3PM code, to increase the width of a detecting window and to suppress or remove a DC component or a low frequency component by converting an input signal into a code word inserting one or more ''0''s between ''1'' and ''1'' to attain NRZI conversion. CONSTITUTION:An inputted NRZ signal is divided for every M (positive integer) bits and the M bits are converted into a code word consisting of N (M

12. 发明专利

JPS60669A MODULATION RECORDING CIRCUIT OF DIGITAL SIGNAL 失效
公开(公告)号：JPS60669A
公开(公告)日：1985-01-05
申请号：JP10788183
申请日：1983-06-17
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： IZUMIDA MORIJI , MITA SEIICHI , KOUNOUE AKIHIKO , ROKUTA MORIHITO , KANEDA HIDEHIRO , SHIONO HIROSHI
IPC分类号： G11B20/14 , G11B20/16
摘要： PURPOSE:To limit the consecution of a same code to a prescribed value or below by adding a redundancy one bit so as to control a DSV in converting an NRZ signal into an NRZI signal and stopping the control of the DSV when a specific pattern is generated. CONSTITUTION:A serial data Si in 8-bit is inputted to to a serial parallel converting circuit 1, where the data is converted into a parallel data A. The data A is fetched in a latch circuit 2 and the output data B of the latch circuit 2 is fetched to a latch circuit 3. As a result, the data is arranged in the order of C, B, A being a preceding word data. Then the latch data A, B, C are inputted to an entire zero detecting circuit 5 so as to detect the number of consecutive ''0''. A read only memory ROM is worked as a 8-9 NRZI converting circuit 4. If the output data F of the entire zero detecting circuit 5 is ''1'', the control of the DSV is stopped so as to form the redundancy bit as ''1'' and the NRZI conversion is applied by specifying the ROM table, then the consecutive ''0'' after the conversion is inhibited, the bits are limited to a maximum 12-bit and the DSV is controlled.

13. 发明专利

JPH02135882A VIDEO TAPE RECORDER 失效
公开(公告)号：JPH02135882A
公开(公告)日：1990-05-24
申请号：JP28877588
申请日：1988-11-17
申请人： HITACHI LTD
发明人： TSUJI HIDEAKI , NISHIJIMA HIDEO , ONO KOICHI , OWASHI HITOAKI , SEKIYA MASATAKA , ROKUTA MORIHITO
IPC分类号： H04N5/7826 , H04N5/782 , H04N5/91 , H04N5/93 , H04N5/937
摘要： PURPOSE:To attain the synthesis switching of a screen in the joint of two different scenes which are consecutively recorded in one magnetic tape by providing a control circuit controlling a memory and a screen synthesis switching circuit when a position designation means detect a position designation signal. CONSTITUTION:The control circuit 50 controls the screen synthesis switching circuit 11 and outputs a video signal which is read from the memory 9 among two video signals inputted to the screen synthesis switching circuit 11. Consequently, a picture immediately before the joint as a still picture is outputted from the screen synthesis switching circuit 11. Then, the control circuit 50 controls the screen synthesis switching circuit 11 and switches and outputs the video signal reproduced from the video signal which has been read from the memory 9 while screen synthesis and switching such as cross fade and wipe are performed. Thus, the screen can be switched from one scene to the other in the joint of two different scenes, which are consecutively recorded one magnetic tape, while screen synthesis and switching such as cross fade and wipe used in actual television broadcasting is performed.

14. 发明专利

JPH0244990A METHOD AND DEVICE FOR VIDEO SIGNAL PROCESSING 失效
公开(公告)号：JPH0244990A
公开(公告)日：1990-02-14
申请号：JP19463588
申请日：1988-08-05
申请人： HITACHI LTD
发明人： OWASHI HITOAKI , OTSUBO HIROYASU , SEKIYA MASATAKA , MITSUBE AKISHI , NISHIJIMA HIDEO , ROKUTA MORIHITO
IPC分类号： H04N9/67
摘要： PURPOSE:To prevent deterioration in picture quality due to residual amount of a chrominance signal into a luminance signal even if the chrominance signal remains in the luminance signal by selecting the same frequency to a memory write clock and a read clock. CONSTITUTION:The title device consists of a video signal input terminal 1, a Y/C separation circuit 2, a demodulation circuit 3, an A/D conversion circuit 4, a signal processing circuit 5, a memory 6, a D/A conversion circuit 7, a modulation circuit 8, a mixing circuit 9, an output terminal 10, a switching circuit 11, a synchronizing separator circuit 12, a write clock generating circuit 13, a read clock generating circuit 14, a switching circuit 15, a write control circuit 16, a read control circuit 17, an identification circuit 18 and a microcomputer 19. The the frequency for the memory write and read clocks is made coincident to prevent expansion of the time base of a video signal due to the signal processing. Thus, no time base expansion and compression are caused in the chrominance signal resident in the luminance signal. Then the deterioration in the picture quality due to the remained chrominance signal in the luminance signal is not caused.

15. 发明专利

JPH01302970A MAGNETIC RECORDING/REPRODUCING DEVICE 失效
公开(公告)号：JPH01302970A
公开(公告)日：1989-12-06
申请号：JP13134788
申请日：1988-05-31
申请人： HITACHI LTD
发明人： ONO KOICHI , NISHIJIMA HIDEO , SEKIYA MASATAKA , OWASHI HITOAKI , ROKUTA MORIHITO
IPC分类号： H04N5/265 , G11B20/02 , H04N5/93 , H04N5/937
摘要： PURPOSE:To synchronize a regenerated video signal and an input video signal through the use of a small capacity memory by controlling the output phase of a servo reference signal generation circuit by the vertical synchronizing signal of the input video signal. CONSTITUTION:The phase of the regenerated video signal E is controlled on the basis of reference signals C, C' from the servo reference signal generation circuit 13, and besides, the circuit 13 is controlled by the vertical synchronizing signal of the input video signal F through a read control circuit 20. Therefore, phase difference between the regenerated video signal G and the signal F can be kept nearly constant. On the other hand, the signal E determines the write timing of the memory circuit 21 through a synchronizing separation circuit 18 and a write control circuit 19, and the signal F determines the read timing of a circuit 11 through a signal separation circuit 23 and the circuit 20, and the phase difference between the signal E and the signal F becomes nearly constant. Therefore, memory capacity necessitated for the circuit 21 have only to be capacity capable of absorbing jitter.

16. 发明专利

JPS61269532A PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPS61269532A
公开(公告)日：1986-11-28
申请号：JP11043785
申请日：1985-05-24
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： IZUMIDA MORIJI , DOI NOBUKAZU , MITA SEIICHI , ROKUTA MORIHITO , SHIONO HIROSHI
IPC分类号： H03L7/14 , H03L7/06 , H04L7/033 , H04N5/93
摘要： PURPOSE:To obtain a voltage controlled oscillation output signal with less affected by dropout by switching an input signal during dropout period into an output signal in a phase locked loop control circuit to which a discontinuous signal is inputted due to dropout. CONSTITUTION:A selector circuit 10 selecting the output of a tank circuit 2 and an output of a voltage controlled oscillation circuit 6 is added. The circuit 10 is phase-locked in loop by an output of an envelope detection circuit 7, the output of the circuit 2 while no dropout exists selects the output of the circuit 16 when dropout takes place. An output 11 of the circuit 10 and an output 12 of the circuit 6 input to a phase comparator 3 to generate an error voltage 13 proportional to the phase difference, after the voltage is smoothed by an LPF 5, the result is inputted to the circuit 6. The circuit 6 outputs a signal 12 having a frequency proportional to the input voltage 14 and feeds back it to the circuit 10 and the comparator 3.

17. 发明专利

JPS60178783A DIGITAL VIDEO RECORDING SYSTEM 失效
公开(公告)号：JPS60178783A
公开(公告)日：1985-09-12
申请号：JP3354384
申请日：1984-02-24
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： UMEMOTO MASUO , MITA SEIICHI , MICHIKAWA YUUICHI , IZUMIDA MORIJI , KATAYAMA HITOSHI , ROKUTA MORIHITO , KANEDA HIDEHIRO
IPC分类号： H03M7/14 , G11B5/09 , G11B20/14 , H04L25/49 , H04N5/91 , H04N5/92 , H04N9/804
摘要： PURPOSE:To reduce generating frequency of signal errors due to a pttern peak shift, etc., by converting a pattern into such a pattern that the prescribed number or more of ''1'' or ''0'' will not continue in terms of 8-8 mapping table for decreasing a DC component at the time of magnetic recording. CONSTITUTION:First, a pattern of n max=6 (nr=3; ns=3) is preferentially used as a 8-8 mapping table for a Y signal, and a number of quantized levels 196 are secured. For a pattern of remaining four levels, a pattern having six numbers of ''1'' among n max=7 or 8 bits is selectively used and storedin tables 8, 9 and 10. Since the necessary number of quantized levels is 224 for a mapping table for signals C1 and C2, n max=8 (nr=ns

18. 发明专利

JPS60667A DIGITAL SIGNAL MODULATING SYSTEM 失效
公开(公告)号：JPS60667A
公开(公告)日：1985-01-05
申请号：JP10788283
申请日：1983-06-17
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： IZUMIDA MORIJI , MITA SEIICHI , KOUNOUE AKIHIKO , TAKAGI HITOSHI , ROKUTA MORIHITO , KANEDA HIDEHIRO , FUJIMURA NOBUAKI , SHIONO HIROSHI
IPC分类号： H03M7/00 , G11B20/14
摘要： PURPOSE:To limit the consecution of a same code and also to eliminate a DC and a low frequency component by adding a slight redundancy bit in a circuit converting a data of input (2n-1)-bit into a data in 2n-bit. CONSTITUTION:The conversion of 7-bits into 8-bits is exemplified. In fig., 1 is a serial parallel converting circuit, 2 is read only memory ROM storing a conversion table, 3 is a parallel serial conversion circuit and 4 is a DSV calculating circuit. An input data is converted into a parallel data P (7-bit) by the serial parallel converting circuit 1 and this data is inputted to the ROM 2. Further, a data S representing the pluse or minus sign of an accumulated value DSV of the weight of past data is inputted to this ROM. The converted data Q and the weight R of the data are calculated and outputted based on 8 data. The converted data q is inputted to the parallel serial converting circuit 3, where the data is outputted after being converted into a serial data.

19. 发明专利

JPS59186106A Digital signal recording circuit 失效
标题翻译：数字信号记录电路
公开(公告)号：JPS59186106A
公开(公告)日：1984-10-22
申请号：JP6084283
申请日：1983-04-08
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： IZUMIDA MORIJI , MITA SEIICHI , KOUNOUE AKIHIKO , TAKAGI HITOSHI , ROKUTA MORIHITO , SHIONO HIROSHI , KANEDA HIDEHIRO
IPC分类号： G11B20/14 , G11B20/10
CPC分类号： G11B20/10203
摘要： PURPOSE:To suppress an average DC component without prolonging consecution of 0 or 1 by adding a redundancy bit to decrease the consecution of 0 or 1 and a redundancy bit to eliminate a DC component so as to decrease the rate of rise of a data rate. CONSTITUTION:An NRZ signal is converted into an NRZI signal so as to prevent the expansion of error due to blocking. The 1st modulation circuit 20 adds the 1st redundancy bit and controls the block so that 1s share over a half of the block. The 2nd modulation circuit 30 adds the 2nd redundancy bit and controls the block so that the accumulative value of weight closes to 0. The NRZI data is a code where preceding and succeeding bits are related to each other and two degrees of freedom are given by inserting two redundancy bits between blocks. Thus, the DC component is eliminated by using comparatively less number of redundancy bits and further, the consecution of 1s and 0s is decreased.
摘要翻译：目的：通过添加冗余位来减少0或1的连续性来抑制平均直流分量，而不延长连续使用0或1，并且冗余位消除直流分量，以降低数据速率的上升率。构成：NRZ信号被转换成NRZI信号，以防止由于阻塞造成的误差扩大。第一调制电路20添加第一冗余位并控制块，使得1s共享该块的一半以上。第二调制电路30加上第二冗余位，并控制块，使得重量的累计值接近0. NRZI数据是前后位彼此相关的代码，并且通过插入来给出两个自由度块之间的两个冗余位。因此，通过使用相对较少数量的冗余位来消除DC分量，并且还减少了1s和0s的连续性。

20. 发明专利

JPH11231854A METHOD AND DEVICE FOR IMAGE DISPLAY 失效
公开(公告)号：JPH11231854A
公开(公告)日：1999-08-27
申请号：JP2859298
申请日：1998-02-10
申请人： HITACHI LTD
发明人： ANDO ATSUKO , ROKUTA MORIHITO
IPC分类号： G09G5/00
摘要： PROBLEM TO BE SOLVED: To automatically set the refresh rate value of a display to an optimum value in conformity with a drawing and processing performance for an image to be drawn. SOLUTION: A graphics control part 126 calculates a time (drawing processing time) spent for writing in a frame memory 124. The result of the calculation is used for making judgement as to whether a refresh rate needs to be modified. Also, a refresh rate processing part 127 makes judgement as to whether a status necessary for the change of the rate is detected for a plurality of times. When the status is detected, the refresh rate processing part 127 adjusts a refresh rate upward or downward. As a result, the refresh rate is set so as to optimize the drawing performance of a display 131 and the deterioration of the drawing performance of the display 131 is prevented.

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