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1. 发明专利

JPH07105589A TIME CHANGING SYSTEM FOR TIMER VIDEO RECORDING DEVICE 失效
公开(公告)号：JPH07105589A
公开(公告)日：1995-04-21
申请号：JP24656893
申请日：1993-10-01
申请人： HITACHI LTD
发明人： ROKUTA MORIHITO
IPC分类号： H04N5/7826 , G11B15/02 , H04N5/76
摘要： PURPOSE:To make the time prolongation of a timer video recording simple without changing the broadcasting system of a broadcasting station. CONSTITUTION:This system is provided with a system control circuit 1 controlling the whole of a system, a motor control circuit 2 driving a motor, a display circuit 3 displaying prolongations and cautions, an input circuit 4 performing the inputtings of prolonging information and a tape running system circuit 5 monitoring a tape running state. When a prolonging information is inputted from the input circuit 4, the system control circuit 1 prolongs a reservation completing time and also makes the motor control circuit 2 operate and calculates the remaining time of a tape with information from the tape running system circuit 5 and then displays a caution on the display circuit 3 in a case that the video recording of the whole of a reserved time is impossible and controls a tape speed optimally in a case that the recording is possible.

2. 发明专利

JPH0562490B2 失效
公开(公告)号：JPH0562490B2
公开(公告)日：1993-09-08
申请号：JP11948784
申请日：1984-06-11
申请人： HITACHI LTD , HITACHI ELECTRONICS , HITACHI VIDEO ENG
发明人： MITA SEIICHI , IZUMIDA MORIJI , MICHIKAWA JUICHI , KATAYAMA HITOSHI , SHIONO HIROSHI , TAKAGI HITOSHI , ROKUTA MORIHITO , DOI NOBUKAZU
IPC分类号： G11B20/10 , H03K5/01
摘要： An apparatus for regenerating original signals comprising: means for introducing a first signal that is produced as an original signal passes through a system that cuts off predetermined frequencies; a first circuit means 30 which produces a third signal obtained on an open loop responsive to said first signal and a second signal which is regenerated from a signal of a predetermined frequency that is cut off by said system; and a second circuit means 12 which regenerates the original signal by converting said third signal into a binary signal.

3. 发明专利

JPH03177179A TIME BASE COLLECTOR 失效
公开(公告)号：JPH03177179A
公开(公告)日：1991-08-01
申请号：JP31539789
申请日：1989-12-06
申请人： HITACHI LTD
发明人： FUJII YUKIO , OKU MASUO , ABE HIROCHIKA , TAKAHASHI SUSUMU , ROKUTA MORIHITO
IPC分类号： H04N5/956 , G11B20/02 , H04N5/95 , H04N9/89 , H04N9/896
摘要： PURPOSE:To surely and accurately extract a desired data and to attain picture reproduction without position fluctuation by replacing a video signal read from a memory into a composite synchronizing signal generated by a reference synchronizing signal generator. CONSTITUTION:When a blanking signal BLNK is fed to a switch 16, it is thrown to the position of Y to select a composite synchronizing signal CSYNC. Thus, a composite synchronizing signal CSYNC is outputted from an output terminal 12 in place of a horizontal synchronizing signal of a video signal Vout, a vertical synchronizing signal and an equalizing pulse. Thus, the composite synchronizing signal CSYNC of the video signal Vout is replaced into the composite synchronizing signal CSYNC synchronously with it and a horizontal synchronizing signal and a vertical synchronizing signal with excellent waveform in the video signal Vout obtained at the output terminal 12 are set at a correct position. Thus, the deviation in the vertical direction of a reproduced picture is prevented on the monitor screen and a desired data added in a vertical blanking period of the video signal Vout is surely and accurately extracted.

4. 发明专利

JPS61113166A Time axis correction device in digital information reproduction system 失效
标题翻译：数字信息生成系统中的时间轴修正装置
公开(公告)号：JPS61113166A
公开(公告)日：1986-05-31
申请号：JP23250384
申请日：1984-11-06
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： UMEMOTO MASUO , ETO YOSHIZUMI , KANEDA HIDEHIRO , ROKUTA MORIHITO
IPC分类号： G11B20/10 , G11B20/12 , G11B27/30 , H04L7/00 , H04N5/956
CPC分类号： H04N5/956 , G11B20/10 , G11B20/1201 , G11B27/3027
摘要： PURPOSE: To enhance the reliability by preventing malfunction caused by code error due to various factors including a dropout.
CONSTITUTION: An address 603 generated in accordance with a block number 601 read out and sub-block number 602 is compared (606) with an expected address 604. If they coincide, a selector 611 selects the expected address. In case they do not coincide, a calculated value n is added by '1', and if the result does not reach the specified value N
0 , the expected address 604 is selected. However, if the incoincidence continuously occurs for specific N
0 times, a C
1 detection circuit 609 detects it, and then the selector 611 selects the expected address. When C
1 pattern is not detected, the block number and the sub-block number read out are regarded correct, and the address correspond with them is selected by the selector 611.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过防止由于各种因素导致的代码错误导致的故障，从而提高可靠性。构成：将根据读取的块号601生成的地址603和子块号602与预期地址604进行比较（606）。如果它们一致，则选择器611选择预期地址。在不一致的情况下，将计算值n加上“1”，如果结果未达到规定值N0，则选择预期地址604。然而，如果不确定性连续发生特定的N0次，则C1检测电路609检测它，然后选择器611选择预期的地址。当未检测到C1模式时，读出的块号和子块号被认为是正确的，并且由选择器611选择与它们对应的地址。

5. 发明专利

JPS60106074A DIGITAL MAGNETIC PICTURE RECORDER 失效
公开(公告)号：JPS60106074A
公开(公告)日：1985-06-11
申请号：JP21235383
申请日：1983-11-14
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： UMEMOTO MASUO , MITA SEIICHI , IZUMIDA MORIJI , ROKUTA MORIHITO , MIYAZAKI SHINICHI
IPC分类号： G11B20/12 , G11B20/10 , H04N5/91 , H04N5/92
摘要： PURPOSE:To enhance equilibrium property of digital information to be recorded without a rise of a bit rate by converting and recording a digital information pattern of two samples into the digital pattern in which 1 and 0 is approximately balanced. CONSTITUTION:16 bits in a block are distributed to Channel 6 by a distributing circuit 4. In such a way a bit rate drops to one-sixth, and the bit rate becomes 70Mbit/sec, which can be used on a commercial basis. Since an output of the distributing circuit 4 is a parallel output of 16 bits, it is converted into a series output of 16 bits, it is converted into a series output by parallel/serial convertors 5-1-5-6 and the series output is recorded on a magnetic tape through heads 6-1-6-6. In order to reproduce, a reverse process of the recording is constituted. Since 16 bits/16 bits convertor 3 is of large capacity of 2 X16=1,048,576 bits, the convertor 3 cannot be constituted with one unit of ROM memory, and utilizes four units of the ROM memory with 65,536X4 bits (so called 256k bits).

6. 发明专利

JPH02134987A PICTURE EDITING DEVICE 失效
公开(公告)号：JPH02134987A
公开(公告)日：1990-05-23
申请号：JP28765688
申请日：1988-11-16
申请人： HITACHI LTD
发明人： YAMAUCHI HIROTO , ROKUTA MORIHITO
IPC分类号： H04N5/265
摘要： PURPOSE:To control timing for starting wiping and to stabilize a wiping operation by clamping waveform for switching a screen in the title device to wipe two video signals and switch the picture. CONSTITUTION:The device is the picture editing device to wipe the two video signals and switch the picture, separates two or more wiping waveforms for switching the picture in a synchronization separator circuit 30, forms the separated waveforms in waveform generating circuits 40 and 50, and clamps the formed waveforms in a clamping circuit 90 under the same voltage. Thus, even when the DC levels of the two waveforms are different to some extent, or the DC levels are unstable, the DC levels of the two waveforms become the same level since the two waveforms are clamped, the timing for starting wiping can be made coincident, and the operation can be stabilized.

7. 发明专利

JPH02122788A COLOR VIDEO SIGNAL PROCESSING METHOD 失效
公开(公告)号：JPH02122788A
公开(公告)日：1990-05-10
申请号：JP27444088
申请日：1988-11-01
申请人： HITACHI LTD
发明人： OWASHI HITOAKI , ONO KOICHI , NISHIJIMA HIDEO , SEKIYA MASATAKA , ROKUTA MORIHITO
IPC分类号： H04N9/79 , H04N9/64 , H04N9/74
摘要： PURPOSE:To prevent a color flicker at the time of processing a still picture by providing a noise suppressing means using a memory as a delay means, and always noise-processing an inputted luminance signal and a color difference signal. CONSTITUTION:A signal processing circuit 9 and a memory 10 having memory capacity for at least one field constitute a noise suppressing circuit. Normally the luminance signal from an A/D converter 4 and the color difference signal from an A/D converter 5 are written into the memory 10, they are read by delaying by one field, and the read signals, the luminance signal to be inputted and the color difference signal execute a noise eliminating processing. In an editing period, writing to the memory 10 is stopped, a luminance signal Y' and a chrome signal C' repeatedly read from the memory 10, and a luminance signal Y and a chroma signal C outputted from a Y/C separating circuit 2 are supplied to an effector circuit 15, processed, and supplied to an adding circuit 16. Thus, the color flicker of the still picture in the editing time can be suppressed.

8. 发明专利

JPS63283281A VIDEO OUTPUT DEVICE 失效
公开(公告)号：JPS63283281A
公开(公告)日：1988-11-21
申请号：JP11681587
申请日：1987-05-15
申请人： HITACHI LTD
发明人： ROKUTA MORIHITO
IPC分类号： H04N5/265 , H04N5/45
摘要： PURPOSE:To output a video signal resistant to external noise even in a case where no signal exists on a master picture and the cycle of whose synchronizing signal coincides with the cycle of an ordinary television signal, by using the synchronizing signal of a slave picture side by detecting the fact of the no signal of the master picture when it occurs, in the case that the slave picture is inserted in the master picture. CONSTITUTION:From inputted master picture and slave picture, the synchronizing signals are extracted by synchronization separating circuits 12 and 15, and are inputted to a synchronizing signal switching circuit 14. The synchronizing signal switching circuit 14 switches the synchronizing signal to that of the slave picture only when no signal exists on the master picture by a master picture no signal detection circuit 13. A signal made into the slave picture by a slave picture conversion circuit 16 is synthesized with the master picture generally at a picture synthesizing circuit 11, and when no signal exists on the master picture, only a slave picture forming signal is outputted. Next, a synchronizing signal detector 21 detects the synchronizing signal from the master picture. The signal is stored in a capacitor, and increases the base potential of a transistor 22, and turns ON the transistor. As a matter of course, the transistor is burned OFF at the time of no signal on the master picture. By turning OFF the transistor, a vertical synchronizing signal VD is switched from a master VD to a slave VD by a synchronizing signal change-over switch 23.

9. 发明专利

JPS61248269A METHOD FOR TRANSMITTING DIGITAL SIGNAL AND ITS PROCESSOR 失效
公开(公告)号：JPS61248269A
公开(公告)日：1986-11-05
申请号：JP8861885
申请日：1985-04-26
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： IZUMIDA MORIJI , MITA SEIICHI , DOI NOBUKAZU , ROKUTA MORIHITO , SHIONO HIROSHI , KANEKO MAMORU , INUI FUYUKI
IPC分类号： G11B20/18 , G11B20/10 , H04L1/00
摘要： PURPOSE:To improve the reliability of a transmission signal between recording and reproducing devices for a digital signal at the transmission of the signal by transmitting the output of a reproducing signal processing means through a recording signal processing means in an equipment on a transmitting side, and receiving the transmitted signal by a recording signal processing means through a reproducing signal processing means in the equipment on a receiving side. CONSTITUTION:Digital data 6a detected and corrected by a reproducing signal processing circuit 11a are inputted to a recording signal processing circuit 12a to add an additional signal such as an error correcting parity and a synchronizing pattern to the input signal 6a and the added signal is outputted to a reproducing signal processing circuit 11b on the recording side. The circuit 11b detects and corrects an error generated in a transmission line A at the time of transmission from a digital VTR 10a to a VTR 10b and outputs the corrected signal to a recording signal processing circuit 12b as an original digital signal 7b. The circuit 12b adds an additional signal such as an error correcting parity and a synchronizing pattern to the digital signal 7b sent from the circuit 11b and outputs the added signal to a magnetic recording/reproducing device 13b. The device 13 records a signal 8b outputted from the circuit 12b in a recording medium.

10. 发明专利

JPS61242424A ERROR CORRECTING METHOD 失效
公开(公告)号：JPS61242424A
公开(公告)日：1986-10-28
申请号：JP8431985
申请日：1985-04-19
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： IZUMIDA MORIJI , DOI NOBUKAZU , MITA SEIICHI , SAITO AKIRA , ROKUTA MORIHITO , SHIONO HIROSHI
IPC分类号： H03M13/00
摘要： PURPOSE:To correct occurring errors and to reduce missing by adding the 1st pointer to an uncorrectable word when decoding is performed at an initial state and adding the 2nd pointer to some of uncorrectable words without error correction when an error in one word is a pattern other then a specific pattern. CONSTITUTION:A data sequence 100 inputted to an input terminal 10 is supplied to a syndrome arithmetic circuit 210 to calculate syndromes S0, S1, S2, and S3. For example, the syndrome S0 is obtained by EORing (exclusively ORing) data 00,01...08, and 09 with words having parity data B00, B01, B02, and B03 and constituted a one-byte (8-bit) signal. Those four syndromes S0, S1, S2, and S3 (201) are outputted to an error position and error pattern arithmetic circuit 220. The error position and error pattern arithmetic circuit 220 calculates an error occurrence position and an error pattern from the syndromes S0, S1, S2, and S3.

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