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1. 发明专利

JPS5856225A MAGNETIC HEAD DEVICE 失效
公开(公告)号：JPS5856225A
公开(公告)日：1983-04-02
申请号：JP15355881
申请日：1981-09-30
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： KIRINO TOORU , MITA SEIICHI , KOUNOUE AKIHIKO , NAGAHARA SHIYUUSAKU , UMEMOTO MASUO
IPC分类号： G11B5/48 , G11B5/53
摘要： PURPOSE:To ensure an easy and highly precise working of a magnetic head device and at the same time to facilitate the accurate running of each head chip, by distributing plural head chips on a substrate and setting property the attachment surface of the substrate and the gap direction of the head chip. CONSTITUTION:The attachment surface 19 of a head substrate 18 is set oblique to the sliding direction B of a tape in order to ensure the running at the prescribed track position for gaps 15g-17g. For this purpose, the differences of levels l1 and l2 are provided. The 15g-17g gaps of head chips 15-17 are set rectangular to the direction B in order to obtain a prescribed value for the recording track width l3 on the tape. Plural grooves having depth l4 are formed to the substrate 18 to facilitate the distribution of chips 15-17 at the prescribed positions on the substrate 18. Furthermore, the head chips are put close to each other to decrease the size of the window and to reduce the damage of the tape.

2. 发明专利

JPS60669A MODULATION RECORDING CIRCUIT OF DIGITAL SIGNAL 失效
公开(公告)号：JPS60669A
公开(公告)日：1985-01-05
申请号：JP10788183
申请日：1983-06-17
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： IZUMIDA MORIJI , MITA SEIICHI , KOUNOUE AKIHIKO , ROKUTA MORIHITO , KANEDA HIDEHIRO , SHIONO HIROSHI
IPC分类号： G11B20/14 , G11B20/16
摘要： PURPOSE:To limit the consecution of a same code to a prescribed value or below by adding a redundancy one bit so as to control a DSV in converting an NRZ signal into an NRZI signal and stopping the control of the DSV when a specific pattern is generated. CONSTITUTION:A serial data Si in 8-bit is inputted to to a serial parallel converting circuit 1, where the data is converted into a parallel data A. The data A is fetched in a latch circuit 2 and the output data B of the latch circuit 2 is fetched to a latch circuit 3. As a result, the data is arranged in the order of C, B, A being a preceding word data. Then the latch data A, B, C are inputted to an entire zero detecting circuit 5 so as to detect the number of consecutive ''0''. A read only memory ROM is worked as a 8-9 NRZI converting circuit 4. If the output data F of the entire zero detecting circuit 5 is ''1'', the control of the DSV is stopped so as to form the redundancy bit as ''1'' and the NRZI conversion is applied by specifying the ROM table, then the consecutive ''0'' after the conversion is inhibited, the bits are limited to a maximum 12-bit and the DSV is controlled.

3. 发明专利

JPS60667A DIGITAL SIGNAL MODULATING SYSTEM 失效
公开(公告)号：JPS60667A
公开(公告)日：1985-01-05
申请号：JP10788283
申请日：1983-06-17
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： IZUMIDA MORIJI , MITA SEIICHI , KOUNOUE AKIHIKO , TAKAGI HITOSHI , ROKUTA MORIHITO , KANEDA HIDEHIRO , FUJIMURA NOBUAKI , SHIONO HIROSHI
IPC分类号： H03M7/00 , G11B20/14
摘要： PURPOSE:To limit the consecution of a same code and also to eliminate a DC and a low frequency component by adding a slight redundancy bit in a circuit converting a data of input (2n-1)-bit into a data in 2n-bit. CONSTITUTION:The conversion of 7-bits into 8-bits is exemplified. In fig., 1 is a serial parallel converting circuit, 2 is read only memory ROM storing a conversion table, 3 is a parallel serial conversion circuit and 4 is a DSV calculating circuit. An input data is converted into a parallel data P (7-bit) by the serial parallel converting circuit 1 and this data is inputted to the ROM 2. Further, a data S representing the pluse or minus sign of an accumulated value DSV of the weight of past data is inputted to this ROM. The converted data Q and the weight R of the data are calculated and outputted based on 8 data. The converted data q is inputted to the parallel serial converting circuit 3, where the data is outputted after being converted into a serial data.

4. 发明专利

JPS60668A DIGITAL SIGNAL RECORDING CIRCUIT 失效
公开(公告)号：JPS60668A
公开(公告)日：1985-01-05
申请号：JP10788383
申请日：1983-06-17
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： ROKUTA MORIHITO , MITA SEIICHI , IZUMIDA MORIJI , KOUNOUE AKIHIKO , FUJIMURA NOBUROU , TAKAGI HITOSHI , SHIONO HIROSHI , KANEDA HIDEHIRO
IPC分类号： G11B20/14
摘要： PURPOSE:To constitute a code with less consecutive ''0'' and without a DC component by providing a block conversion so as to reduce the consecutive ''0'' or ''1'' and adding a redundancy so as to eliminate the DC component and low frequency component. CONSTITUTION:Suppose that a data D1 in 16-bit is inputted to a serial parallel converting circuit 210, the data of first 8-bit in 16 bits is subject to NRZI conversion by using ''0'' as a redundancy bit at an ROM converting circuit 211 and the data 9-bit and the 4-bit binary-coding the weight information of the data is outoutped. Further, the data in latter 8-bit is processed similarly in an ROM converting circuit 212. The weight 4-bit outputted from the two ROM converting circuits 211 and 212 is added at a weight adder 214 and the outputted data becomes the weight 5-bit to the input data 16-bit. The weight 5-bit of the converted data and a DSV 5-bit are added at a weight accumulating value operating circuit 215 and when the inverting information is outputted, the waveform of E1 is inverted into the waveform of E2 so as to form a final data.

5. 发明专利

JPS5994214A DIGITAL SIGNAL RECORDER 失效
公开(公告)号：JPS5994214A
公开(公告)日：1984-05-30
申请号：JP20366782
申请日：1982-11-22
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： IZUMIDA MORIJI , MITA SEIICHI , KOUNOUE AKIHIKO , ROKUTA MORIHITO , KANEDA HIDEHIRO , SHIONO HIROSHI
IPC分类号： G11B20/14
摘要： PURPOSE:To eliminate the DC component and at the same time to prevent the extension of an error by increasing the data rate up to (M+1)/M and inserting a redundant bit to convert it into an NRZI signal. CONSTITUTION:An output clock CK2 synchronized with an input clock CK1 is generated by a PLL, etc. in order to convert the input data rate into an output data rate. The clock CK2 has a frequency of (M+1)/M times as high as the clock CK1 and produces two type of data series containing ''0'' and ''1'' added at the head to M units of input data (NRZ). These data are fed to a pattern generating circuit 2 to produce the data of each NRZI, and these data are supplied to a selection circuit 3. The circuit 3 selects either one of both data. For decision of this selection, a weight deciding circuit 4 calculates previously the weight cumulative value DSV of blocks up to the 1-block preceding one. It is possible to select and deliver the data having the negative weight and the data having the positive weight delivered from the circuit 2 when the value DSV is positive and negative respectively.

6. 发明专利

JPS58150113A MAGNETIC RECORDER WITH MULTICHANNEL HEAD 失效
公开(公告)号：JPS58150113A
公开(公告)日：1983-09-06
申请号：JP3246382
申请日：1982-03-03
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： MITA SEIICHI , FUJIWARA HIDEO , KOUNOUE AKIHIKO , KUMASAKA TAKAYUKI
IPC分类号： G11B5/008 , G11B5/09 , G11B5/53 , G11B20/02 , G11B20/10 , H04N5/7826 , H04N5/926
摘要： PURPOSE:To improve recording density by providing multichannel heads to a rotary drum and making disposition and constitution adequate according to the spacings between head chips. CONSTITUTION:Multichannel heads A, B are installed on a rotating drum 1. When the heads A, B scan a magnetic tape T and record television signals, the width of their track loci is C as with each chip. The speed of the magnetic tape and the rotating speeds of the heads are so controlled that the locus of one head of the plural multiheads adjoins successively to each other and n-pieces of >=2 integer of the multichannel heads at which the relations between the track width C drawn by each head chip and inter-track-spacings P attain P/C >=n are installed on the drum, whereby the recording density of the magnetic tape is increased.

7. 发明专利

JPS6025005A REGENERATIVE PREAMPLIFIER CIRCUIT 失效
公开(公告)号：JPS6025005A
公开(公告)日：1985-02-07
申请号：JP13276283
申请日：1983-07-22
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： SHIONO HIROSHI , MITA SEIICHI , KOUNOUE AKIHIKO , IZUMIDA MORIJI , KANEDA HIDEHIRO , TAKAGI HITOSHI , ROKUTA MORIHITO
IPC分类号： G11B5/02 , H04N5/92
摘要： PURPOSE:To reproduce both a digital signal and a conventional FM signal through the same circuit by switching a frequency compensating circuit automatically. CONSTITUTION:A switch 5 is off initially. When a frequency component of 4- 5MHz in an FM signal is detected in the output of a preamplifier, the switch 5 is turned on to lower a resonance frequency, and the FM signal is thus regenerated with a good S/N. Namely, the output of the preamplifier 3 is further amplified by an amplifier 17 and the frequency component of 4-5MHz shown in a figure (a) is extracted through a BPF8 from the output, rectified on full-wave basis by a rectifying circuit 9 as shown in a figure (b), and passed through an LPF10 to detect a waveform shown in a figure (c). This is passed through a buffer amplifier 18 and detected by a comparator 11, and a monostable multivibrator 19 generates a pulse in a figure (e), so that the switch 5 is turned on when the pulse is at a high level.

8. 发明专利

JPS5829110A MAGNETIC RECORDING METHOD FOR DIGITAL SIGNAL 失效
公开(公告)号：JPS5829110A
公开(公告)日：1983-02-21
申请号：JP12778081
申请日：1981-08-17
申请人： HITACHI ELECTRONICS
发明人： KOUNOUE AKIHIKO , MITA SEIICHI , KIRINO TOORU , NAGAHARA SHIYUUSAKU
IPC分类号： G11B5/09 , G11B5/035 , G11B20/10 , G11B20/14
摘要： PURPOSE:To increase the size of an eye pattern of a reproducing signal after equalization, by changing the inverted amplitude of a head driving current in accordance with a recording pattern. CONSTITUTION:When driving currents of the same polarity continue at least for 1.5 times the bit period of a digital signal, a current inverting amplitude IV of a current inverting section in which the driving current of the same polarity is started, is kept smaller than the current inverting amplitude IO of the other current inverting sections. Further, the relation between the current inverting amplitude IV and the current inverting amplitude IO is regulated to 1

9. 发明专利

JPS5798111A MAGNETIC RECORDING SYSTEM OF DIGITAL SIGNAL 失效
公开(公告)号：JPS5798111A
公开(公告)日：1982-06-18
申请号：JP17449080
申请日：1980-12-12
申请人： HITACHI ELECTRONICS
发明人： KIRINO TOORU , MITA SEIICHI , KOUNOUE AKIHIKO
IPC分类号： H03M5/04 , G11B20/10 , H04L25/49
摘要： PURPOSE:To improve a bit density by making pulse width narrower than the width of time slot and overlay on the other pulse which is made narrower than the width of the pulse, when a magnetic recording is performed with a ternary code. CONSTITUTION:Original signal B entered from an input terminal 1, is devided into two lines. One is delayed in a delay circuit 2 by time T' and take difference from the original signal B through a subtracter 3 to generate signal C. The signal C further divided into three lines. One of the three is passed through a delay circuit 4 and delayed by the time T'' and takes difference from the other signals by passing through another subtracter 5. Then, the amplitude of the signal is attenuated by passing through alpha attenuator 8 to generate a signal D. The signal D and the other signals which are attenuated to 1-alpha by another attenuator 7, are added by an adder 6 to obtain a signal which has wave form indicated by E at an output terminal 9. Each current wave form of signal pulse has returned to zero in the time slot and therefore, interference between codes can be eliminated to obtain a record with high density.

10. 发明专利

JPS59186106A Digital signal recording circuit 失效
标题翻译：数字信号记录电路
公开(公告)号：JPS59186106A
公开(公告)日：1984-10-22
申请号：JP6084283
申请日：1983-04-08
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： IZUMIDA MORIJI , MITA SEIICHI , KOUNOUE AKIHIKO , TAKAGI HITOSHI , ROKUTA MORIHITO , SHIONO HIROSHI , KANEDA HIDEHIRO
IPC分类号： G11B20/14 , G11B20/10
CPC分类号： G11B20/10203
摘要： PURPOSE:To suppress an average DC component without prolonging consecution of 0 or 1 by adding a redundancy bit to decrease the consecution of 0 or 1 and a redundancy bit to eliminate a DC component so as to decrease the rate of rise of a data rate. CONSTITUTION:An NRZ signal is converted into an NRZI signal so as to prevent the expansion of error due to blocking. The 1st modulation circuit 20 adds the 1st redundancy bit and controls the block so that 1s share over a half of the block. The 2nd modulation circuit 30 adds the 2nd redundancy bit and controls the block so that the accumulative value of weight closes to 0. The NRZI data is a code where preceding and succeeding bits are related to each other and two degrees of freedom are given by inserting two redundancy bits between blocks. Thus, the DC component is eliminated by using comparatively less number of redundancy bits and further, the consecution of 1s and 0s is decreased.
摘要翻译：目的：通过添加冗余位来减少0或1的连续性来抑制平均直流分量，而不延长连续使用0或1，并且冗余位消除直流分量，以降低数据速率的上升率。构成：NRZ信号被转换成NRZI信号，以防止由于阻塞造成的误差扩大。第一调制电路20添加第一冗余位并控制块，使得1s共享该块的一半以上。第二调制电路30加上第二冗余位，并控制块，使得重量的累计值接近0. NRZI数据是前后位彼此相关的代码，并且通过插入来给出两个自由度块之间的两个冗余位。因此，通过使用相对较少数量的冗余位来消除DC分量，并且还减少了1s和0s的连续性。

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