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11. 发明授权

US08405127B2 Method and apparatus for fabricating a heterojunction bipolar transistor 有权
标题翻译：用于制造异质结双极晶体管的方法和装置
公开(公告)号：US08405127B2
公开(公告)日：2013-03-26
申请号：US12034210
申请日：2008-02-20
申请人： Jack O. Chu , Francois Pagette
发明人： Jack O. Chu , Francois Pagette
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/45 , H01L29/66242
摘要： In one embodiment, the invention is a method and apparatus for fabricating a heterojunction bipolar transistor. One embodiment of a heterojunction bipolar transistor includes a collector layer, a base region formed over the collector layer, a self-aligned emitter formed on top of the base region and collector layer, a poly-germanium extrinsic base surrounding the emitter, and a metal germanide layer formed over the extrinsic base.
摘要翻译：在一个实施例中，本发明是用于制造异质结双极晶体管的方法和装置。异质结双极晶体管的一个实施例包括集电极层，形成在集电极层上的基极区域，形成在基极区域和集电极层顶部的自对准发射极，围绕发射极的聚锗外基极和金属形成在外在基础上的锗化物层。

12. 发明授权

US07679164B2 Bipolar transistor with silicided sub-collector 有权
标题翻译：双极晶体管，带硅化子集电极
公开(公告)号：US07679164B2
公开(公告)日：2010-03-16
申请号：US11620242
申请日：2007-01-05
申请人： Francois Pagette , Christian Lavoie , Anna Topol
发明人： Francois Pagette , Christian Lavoie , Anna Topol
IPC分类号： H01L27/102
CPC分类号： H01L29/737 , H01L29/0821 , H01L29/66242
摘要： Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.
摘要翻译：本发明的实施例提供了一种在有源区域中包括集电极的半导体器件; 第一和第二子集电极，所述第一子集电极是与所述集电极相邻的重掺杂半导体材料，所述第二子集电极是靠近所述第一子集电极的硅化副集电极; 以及与所述第二子集电器接触的硅化物到达通道，其中所述第一和第二子集电极和所述硅化物到达通道为所述集电器从所述有源区域收集的电荷提供连续的导电路径。本发明的实施例还提供了制造该方法的方法。

13. 发明申请

US20090283801A1 BIPOLAR TRANSISTOR WITH LOW RESISTANCE BASE CONTACT AND METHOD OF MAKING THE SAME 有权
公开(公告)号：US20090283801A1
公开(公告)日：2009-11-19
申请号：US12535310
申请日：2009-08-04
申请人： Francois Pagette , Kathryn Turner Schonenberg
发明人： Francois Pagette , Kathryn Turner Schonenberg
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/0817 , H01L29/1004 , H01L29/7371
摘要： Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base further includes a first semiconductor material with a first bandgap and a second semiconductor material with a second bandgap that is smaller than the first bandgap.

14. 发明申请

US20090202952A1 SUBLITHOGRAPHIC PATTERNING METHOD INCORPORATING A SELF-ALIGNED SINGLE MASK PROCESS 有权
标题翻译：自动对准单掩模过程的分层方案
公开(公告)号：US20090202952A1
公开(公告)日：2009-08-13
申请号：US12028861
申请日：2008-02-11
申请人： David W. Abraham , Steven E. Steen , Nicholas C.M. Fuller , Francois Pagette
发明人： David W. Abraham , Steven E. Steen , Nicholas C.M. Fuller , Francois Pagette
IPC分类号： G03F7/26
CPC分类号： H01L21/0337 , H01L21/32139
摘要： A method of implementing sub-lithographic patterning of a semiconductor device includes forming a first set of patterned features with a single lithography step, the initial set of patterned features characterized by a linewidth and spacing therebetween; forming a first set of sidewall spacers on the first set of patterned features, and thereafter removing the first set of patterned features so as to define a second set of patterned features based on the geometry of the first set of sidewall spacers; and performing one or more additional iterations of forming subsequent sets of sidewall spacers on subsequent sets of patterned features, followed by removal of the subsequent sets of patterned features, wherein a given set of patterned features is based on the geometry of an associated set of sidewall spacers formed prior thereto, and wherein a final of the subsequent sets of patterned features is characterized by a sub-lithographic dimension.
摘要翻译：实现半导体器件的次光刻图案化的方法包括用单个光刻步骤形成第一组图案化特征，初始的图案化特征集合以其间的线宽和间距为特征; 在所述第一组图案化特征上形成第一组侧壁间隔物，然后移除所述第一组图案特征，以便基于所述第一组侧壁间隔物的几何形状限定第二组图案特征; 以及执行在随后的图案化特征集合上形成随后的一组侧壁间隔物的一个或多个附加迭代，随后移除随后的一组图案化特征，其中给定的一组图案化特征基于相关联的一组侧壁的几何形状间隔物在其之前形成，并且其中后续的一组图案化特征的最后的特征在于亚光刻尺寸。

15. 发明授权

US07388237B2 Local collector implant structure for heterojunction bipolar transistors 有权
标题翻译：用于异质结双极晶体管的局部集电极注入结构
公开(公告)号：US07388237B2
公开(公告)日：2008-06-17
申请号：US11870437
申请日：2007-10-11
申请人： Francois Pagette
发明人： Francois Pagette
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66318 , H01L29/0821 , H01L29/66242 , H01L29/7371 , H01L29/7378
摘要： A bipolar transistor structure includes an intrinsic base layer formed over a collector layer, an emitter formed over the intrinsic base layer, and an extrinsic base layer formed over the intrinsic layer and adjacent the emitter. A ring shaped collector implant structure is formed within an upper portion of the collector layer, wherein the ring shaped collector implant structure is disposed so as to be aligned beneath a perimeter portion of the emitter.
摘要翻译：双极晶体管结构包括在集电极层上形成的本征基极层，在本征基极层上形成的发射体，以及在本征层上形成并邻近发射极的非本征基极层。环形收集器植入结构形成在集电器层的上部内，其中环形收集器植入结构被设置成在发射器的周边部分下方对准。

16. 发明授权

US07180157B2 Bipolar transistor with a very narrow emitter feature 失效
标题翻译：双极晶体管具有非常窄的发射极特性
公开(公告)号：US07180157B2
公开(公告)日：2007-02-20
申请号：US10978775
申请日：2004-11-01
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
IPC分类号： H01L27/082
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/732
摘要： A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped intrinsic emitter formed in the surface of the intrinsic base. An etch stop insulator layer overlies the intrinsic base layer above the collector. A base contact layer of a conductive material overlies the etch stop dielectric layer and the intrinsic base layer. A dielectric layer overlies the base contact layer. A wide window extends through the insulator layer and the base contact layer down to the insulator layer. An island or a peninsula is formed in the wide window leaving at least one narrowed window within the wide window, with sidewall spacers in either the wide window or the narrowed window. The narrowed windows are filled with doped polysilicon forming an extrinsic emitter with the intrinsic emitter formed below the extrinsic emitter in the surface of the intrinsic base.
摘要翻译：双重多晶硅，自对准双极晶体管具有在掺杂半导体衬底中形成的集电极区域，形成在衬底表面上的本征反掺杂基底和形成在本征基底表面的掺杂本征发射极。蚀刻停止绝缘体层覆盖在收集器上方的本征基极层。导电材料的基极接触层覆盖在蚀刻停止介电层和本征基极层之间。电介质层覆盖在基底接触层上。宽窗口延伸穿过绝缘体层和基底接触层向下延伸到绝缘体层。在宽窗口中形成岛或半岛，在宽窗口内留下至少一个变窄的窗口，在宽窗口或狭窄窗口中具有侧壁间隔物。变窄的窗口填充有掺杂的多晶硅，其形成外部发射极，本征发射极在本征基极表面的外部发射极之下形成。

17. 发明授权

US07002221B2 Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 有权
公开(公告)号：US07002221B2
公开(公告)日：2006-02-21
申请号：US10604988
申请日：2003-08-29
申请人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
发明人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
IPC分类号： H01L23/62
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

18. 发明申请

US20050269664A1 BIPOLAR TRANSISTOR WITH ISOLATION AND DIRECT CONTACTS 有权
标题翻译：具有隔离和直接联系的双极晶体管
公开(公告)号：US20050269664A1
公开(公告)日：2005-12-08
申请号：US10709905
申请日：2004-06-04
申请人： David Ahlgren , Gregory Freeman , Francois Pagette , Christopher Schnabel , Anna Topol
发明人： David Ahlgren , Gregory Freeman , Francois Pagette , Christopher Schnabel , Anna Topol
IPC分类号： H01L21/331 , H01L29/737 , H01L29/80
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.
摘要翻译：双极晶体管具有通过金属化直接接触基极 - 集电极结下方的集电极，以降低集电极电阻。消除了常规的通孔和掩埋层以及它们的相关电阻。晶体管非常隔离，几乎消除了良好的衬底电容和器件到器件的漏电流。该结构提供了改进的电性能，包括改进的f T，F max和驱动电流。

19. 发明授权

US06861186B1 Method for backside alignment of photo-processes using standard front side alignment tools 失效
标题翻译：使用标准正面对准工具对照片工艺进行背面对齐的方法
公开(公告)号：US06861186B1
公开(公告)日：2005-03-01
申请号：US10605368
申请日：2003-09-25
申请人： Francois Pagette , Christopher M. Schnabel
发明人： Francois Pagette , Christopher M. Schnabel
IPC分类号： G01B11/00 , G03F7/20 , G03F9/00
CPC分类号： G03F7/70425 , G03F9/7003 , G03F9/7084
摘要： An image of an integrated circuit chip and optical kerf and their mirror image are formed within a single optical field. When a substrate pattern using this process is flipped over or reversed, the processed pattern appears the same as on the first side, equal to its own mirror image. Prior to the backside lithography, a portion of the second side is removed to allow detection of alignment marks on the first side from the second side of the substrate. Once the alignment marks are detected, the lithography continues as though the substrate was not flipped over at all.
摘要翻译：在单个光场内形成集成电路芯片和光学切口及其镜像的图像。当使用该处理的基板图案被翻转或反转时，处理图案显示与第一侧相同，等于其自己的镜像。在背面光刻之前，去除第二侧的一部分以允许从衬底的第二侧检测第一侧上的对准标记。一旦检测到对准标记，就像基片完全没有翻转一样，光刻继续。

20. 发明授权

US07622357B2 Semiconductor device structures with backside contacts for improved heat dissipation and reduced parasitic resistance 有权
标题翻译：具有背面触点的半导体器件结构，用于改善散热和降低的寄生电阻
公开(公告)号：US07622357B2
公开(公告)日：2009-11-24
申请号：US11420282
申请日：2006-05-25
申请人： Kunal Vaed , Jae-Sung Rieh , Richard P. Volant , Francois Pagette
发明人： Kunal Vaed , Jae-Sung Rieh , Richard P. Volant , Francois Pagette
IPC分类号： H01L21/331
CPC分类号： H01L29/7371 , H01L21/76898 , H01L23/481 , H01L29/41708 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The present invention relates to a device structure that comprises a substrate with front and back surfaces, and at least one semiconductor device with a first conductive structure located in the substrate and a second conductive structure located thereover. A first conductive contact is located over the front surface of the substrate and laterally offset from the first conductive structure. The first conductive contact is electrically connected to the first conductive structure by a conductive path that extends: (1) from the first conductive structure through the substrate to the back surface, (2) across the back surface, and (3) from the back surface through the substrate to the first conductive contact on the front surface. Further, a second conductive contact is located over the front surface and is electrically connected to the second conductive structure. The conductive path can be formed by lithography and etching followed by metal deposition.
摘要翻译：本发明涉及一种器件结构，其包括具有前表面和后表面的衬底，以及至少一个具有位于衬底中的第一导电结构的半导体器件和位于其上的第二导电结构。第一导电接触位于衬底的前表面上并且横向偏离第一导电结构。第一导电接触件通过导电路径电连接到第一导电结构，导电路径延伸：（1）从第一导电结构通过基底延伸到背面，（2）延伸穿过后表面，和（3）从背面通过基板的表面到前表面上的第一导电接触。此外，第二导电触点位于前表面上并且电连接到第二导电结构。导电路径可以通过光刻和蚀刻形成，之后是金属沉积。

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