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11. 发明申请

US20130073240A1 SEMICONDUCTOR DEVICE AND TEMPERATURE SENSOR SYSTEM 有权
标题翻译：半导体器件和温度传感器系统
公开(公告)号：US20130073240A1
公开(公告)日：2013-03-21
申请号：US13612656
申请日：2012-09-12
申请人： Tadashi KAMEYAMA , Takanobu Naruse , Takayasu Ito
发明人： Tadashi KAMEYAMA , Takanobu Naruse , Takayasu Ito
IPC分类号： G06F19/00 , G01K7/00
CPC分类号： G01K15/00 , G01K1/00 , G01K7/00 , G01K7/01
摘要： A temperature sensor in a semiconductor device includes a temperature detection circuit for outputting a voltage according to the chip temperature, a reference voltage generating circuit for generating a plurality of reference voltages, and a plurality of voltage comparators for comparing each reference voltage with an output voltage of the temperature detection circuit and thereby generating a chip temperature detection signal configured with multiple bits. Further, the temperature sensor includes a control circuit for controlling the reference voltages generated by the reference voltage generating circuit based on the chip temperature detection signal and thereby changing correspondence between the chip temperature detection signal and the chip temperature to shift a chip temperature detection range. It is possible to expand the chip temperature detection range by changing the correspondence between the chip temperature detection signal and the chip temperature, without increasing the number of voltage comparators.
摘要翻译：半导体器件中的温度传感器包括用于输出根据芯片温度的电压的温度检测电路，用于产生多个参考电压的参考电压产生电路，以及用于将每个参考电压与输出电压进行比较的多个电压比较器从而产生配置有多个位的芯片温度检测信号。此外，温度传感器包括控制电路，用于基于芯片温度检测信号来控制由基准电压产生电路产生的参考电压，从而改变芯片温度检测信号和芯片温度之间的对应关系，以移动芯片温度检测范围。通过改变芯片温度检测信号和芯片温度之间的对应关系，可以扩大芯片温度检测范围，而不增加电压比较器的数量。

12. 发明申请

US20070194433A1 Electronic circuit, a semiconductor device and a mounting substrate 有权
标题翻译：电子电路，半导体器件和安装基板
公开(公告)号：US20070194433A1
公开(公告)日：2007-08-23
申请号：US10592948
申请日：2004-03-19
申请人： Motoo Suwa , Yoshinori Miyaki , Toru Hayashi , Ryoichi Sano , Shigezumi Matsui , Takanobu Naruse , Takashi Sato , Hisashi Shiota
发明人： Motoo Suwa , Yoshinori Miyaki , Toru Hayashi , Ryoichi Sano , Shigezumi Matsui , Takanobu Naruse , Takashi Sato , Hisashi Shiota
IPC分类号： H01L23/12
CPC分类号： H01L23/552 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49171 , H01L2924/00014 , H01L2924/01019 , H01L2924/01055 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0216 , H05K1/023 , H05K1/0246 , H05K1/0248 , H05K1/0298 , H05K1/112 , H05K1/181 , H05K2201/09227 , H05K2201/09236 , H05K2201/09263 , H05K2201/093 , H05K2201/10022 , H05K2201/10159 , H05K2201/10522 , H05K2201/10689 , H05K2201/10734 , Y02P70/611 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electronic circuit includes a first semiconductor device (4) and a second semiconductor device (3) on a mounting substrate. The mounting substrate includes a plurality of mounting substrate lines (201 to 204) which are connected in common with external terminals of a plurality of bits of the first semiconductor device and external terminals of a plurality of bits of the second semiconductor device for every bit. The mounting substrate lines have lengths thereof from the external terminals of the first semiconductor device to the external terminals of the second semiconductor device made unequal for respective bits. Assembling lines (361 to 364) which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. Here, the unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines. According to such a constitution, it is unnecessary to set lengths between the external terminals of the second semiconductor device and the connecting electrodes of the semiconductor chip equal.
摘要翻译：电子电路包括在安装基板上的第一半导体器件（4）和第二半导体器件（3）。安装基板包括与第一半导体器件的多个位的外部端子和第二半导体器件的多个位的外部端子共同连接的多个安装基板线（201〜204）。安装基板线具有从第一半导体器件的外部端子到对于各个位不相等的第二半导体器件的外部端子的长度。从第二半导体器件的外部端子到达半导体芯片的连接电极的组装线（361至364）使其长度对于各个位不相等。这里，安装基板线的不等长度具有抵消装配线的不等长度的关系。根据这种结构，不需要在第二半导体器件的外部端子和半导体芯片的连接电极之间设置长度相等。

13. 发明申请

US20050268130A1 Data processor 有权
标题翻译：数据处理器
公开(公告)号：US20050268130A1
公开(公告)日：2005-12-01
申请号：US11130218
申请日：2005-05-17
申请人： Takanobu Naruse , Hirokatsu Noguchi , Kazuhide Kawade , Yoshiyuki Matsumoto
发明人： Takanobu Naruse , Hirokatsu Noguchi , Kazuhide Kawade , Yoshiyuki Matsumoto
IPC分类号： G06F1/24 , G06F1/04 , G06F1/08 , G06F1/26 , G11C11/407 , H03L7/08
CPC分类号： G06F1/08 , G06F1/24
摘要： It is aimed at providing a data processor capable of suppressing a sudden current change from the viewpoint of a synchronization clock. A data processor 1 comprises a clock pulse generation circuit and a circuit module operating on input clock signal CLKi output from the clock pulse generation circuit. In case of restoration from a power-on reset period or a standby state, the clock pulse generation circuit stepwise changes frequencies of the clock signal from low to high frequencies. This makes it possible to prevent a power supply current from suddenly increasing in case of restoration from the power-on reset period or the standby state.
摘要翻译：旨在提供一种能够从同步时钟的角度抑制突发电流变化的数据处理器。数据处理器1包括时钟脉冲产生电路和对从时钟脉冲发生电路输出的输入时钟信号CLKi进行操作的电路模块。在从上电复位期间或待机状态恢复的情况下，时钟脉冲发生电路逐步地将时钟信号的频率从低频变为高频。这使得可以防止在从上电复位周期或待机状态恢复的情况下电源电流突然增加。

14. 发明申请

US20050253859A1 System LSI and data processing system 审中-公开
标题翻译：系统LSI和数据处理系统
公开(公告)号：US20050253859A1
公开(公告)日：2005-11-17
申请号：US11127133
申请日：2005-05-12
申请人： Yoshitaka Takahashi , Yoshiyuki Matsumoto , Takanobu Naruse , Seiichi Saito , Yoshitaka Takahashi
发明人： Yoshitaka Takahashi , Yoshiyuki Matsumoto , Takanobu Naruse , Seiichi Saito , Yoshitaka Takahashi
IPC分类号： G06F12/00 , G06F12/02 , G06F13/28 , G09G5/00 , G09G5/377 , G09G5/39 , G09G5/393
CPC分类号： G09G5/001 , G09G5/393 , G09G2352/00 , G09G2360/125 , G09G2360/128
摘要： The system LSI has a MCU, a memory access control means equipped with unified memory interfaces with which at least two lines of unified memories A and B can be connected. In the main unit of the data processing system, the purpose of each unified memory is set like “mainly for main storage” or “mainly for display” by software in accordance with the operating status of the data processing system so as to adjust the memory access performance. In addition, the system has a means for specifying the unified memory to access and area therein for every display plane to be controlled by the display control circuit.
摘要翻译：系统LSI具有MCU，具有统一存储器接口的存储器访问控制装置，可以连接至少两行统一存储器A和B。在数据处理系统的主单元中，根据数据处理系统的运行状态，通过软件将每个统一存储器的目的设置为“主要用于主存储”或“主要用于显示”，以便调整存储器访问性能。此外，该系统具有用于指定要由显示控制电路控制的每个显示平面访问的统一存储器和区域的装置。

15. 发明授权

US06701405B1 DMA handshake protocol 失效
标题翻译： DMA握手协议
公开(公告)号：US06701405B1
公开(公告)日：2004-03-02
申请号：US09410927
申请日：1999-10-01
申请人： Vijaya Pratap Adusumilli , Bernard Ramanadin , Atsushi Hasegawa , Shinichi Yoshioka , Takanobu Naruse
发明人： Vijaya Pratap Adusumilli , Bernard Ramanadin , Atsushi Hasegawa , Shinichi Yoshioka , Takanobu Naruse
IPC分类号： G06F1336
CPC分类号： G06F13/28
摘要： A computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory, central processing unit(s) and peripherals. A direct memory access controller (DMAC) is provided with a peripheral-independent interface coupled to the system bus and communicates with the system bus using system bus defined transactions. The DMAC comprises a set of registers. A central processing unit (CPU) configures teh DMAC by loading values into the DMAC registers. The configured DMAC issues an enable signal to a selected system component identified in the DMAC registers. A peripheral request interface is associated with the selected system components and communicates with the system bus using the system bus defined transactions. The selected system component asserts a request signal to the DMAC. In response to the request signal, the DMAC implements a DMA transfer according to the values stored in the DMAC configuration registers. Peripheral-specific signaling is provided to the system component by the peripheral request interface
摘要翻译：具有用于实现DMA传输的简单握手协议的计算机系统。提供一种系统总线，其具有用于耦合到包括存储器，中央处理单元和外围设备的系统组件的多个端口。直接存储器访问控制器（DMAC）具有耦合到系统总线的与外设无关的接口，并使用系统总线定义的事务与系统总线进行通信。 DMAC包括一组寄存器。中央处理单元（CPU）通过将值加载到DMAC寄存器中来配置DMAC。配置的DMAC向DMAC寄存器中标识的所选系统组件发出使能信号。外围设备请求接口与所选系统组件相关联，并使用系统总线定义的事务与系统总线进行通信。所选系统组件向DMAC发出请求信号。响应于请求信号，DMAC根据存储在DMAC配置寄存器中的值实现DMA传输。通过外设请求接口向系统组件提供外设特定的信令

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