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11. 发明授权

US06900495B2 Layer arrangement, memory cell, memory cell arrangement and method for producing a layer arrangement 失效
标题翻译：层布置，存储单元，存储单元布置以及用于生成层布置的方法
公开(公告)号：US06900495B2
公开(公告)日：2005-05-31
申请号：US10314049
申请日：2002-12-04
申请人： Franz Hofmann , R. Johannes Luyken , Wolfgang Rösner
发明人： Franz Hofmann , R. Johannes Luyken , Wolfgang Rösner
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L29/41 , H01L29/78 , H01L27/108
CPC分类号： H01L27/10876 , H01L21/823487 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L29/41 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a layer arrangement, a memory cell, a memory cell arrangement and a method for producing a layer arrangement. The layer arrangement has a monocrystalline substrate, a highly doped region in the substrate and a metallically conductive structure in the highly doped region, a partial region of the highly doped region that is arranged in a surface region of the substrate being monocrystalline.
摘要翻译：本发明涉及层布置，存储单元，存储单元布置和用于制造层布置的方法。层布置具有单晶衬底，衬底中的高度掺杂区域和高掺杂区域中的金属导电结构，该高掺杂区域的部分区域被布置在衬底的表面区域中是单晶的。

12. 发明授权

US07635867B2 Nanotube array and method for producing a nanotube array 失效
标题翻译：纳米管阵列及其制造方法
公开(公告)号：US07635867B2
公开(公告)日：2009-12-22
申请号：US10476663
申请日：2002-05-16
申请人： Andrew Graham , Franz Hofmann , Johannes Kretz , Franz Kreupl , Richard Luyken , Wolfgang Rösner
发明人： Andrew Graham , Franz Hofmann , Johannes Kretz , Franz Kreupl , Richard Luyken , Wolfgang Rösner
IPC分类号： H01L31/0312
CPC分类号： H01L51/0048 , B82Y10/00 , C01B32/05 , G01N27/127 , G11C13/025 , H01L51/0595
摘要： A nanotube array and a method for producing a nanotube array. The nanotube array has a substrate, a catalyst layer, which includes one or more subregions, on the surface of the substrate and at least one nanotube arranged on the surface of the catalyst layer, parallel to the surface of the substrate. The at least one nanotube being arranged parallel to the surface of the substrate results in a planar arrangement of at least one nanotube. Therefore, the nanotube array of the invention is suitable for coupling to conventional silicon microelectronics. Therefore, according to the invention it is possible for a nanotube array to be electronically coupled to macroscopic semiconductor electronics. Furthermore, the nanotube array according to the invention may have an electrically insulating layer between the substrate and the catalyst layer. This electrically insulating layer preferably has a topography which is such that the at least one nanotube rests on the electrically insulating layer at its end sections and is uncovered in its central section. As a result of the surface of the at least one nanotube being partly uncovered, the uncovered surface of the nanotube can be used as an active sensor surface. For example, the uncovered surface of the nanotube can come into operative contact with an atmosphere which surrounds the nanotube array. The electrical resistance of a nanotube changes significantly in the presence of certain gases. Thus because the nanotube is clear and uncovered, the nanotube array can be used in many sensor applications.
摘要翻译：纳米管阵列及其制造方法。纳米管阵列具有衬底，催化剂层，其包括在衬底的表面上的一个或多个子区域，和布置在催化剂层表面上的平行于衬底表面的至少一个纳米管。所述至少一个纳米管平行于衬底的表面布置，导致至少一个纳米管的平面布置。因此，本发明的纳米管阵列适用于与传统的硅微电子耦合。因此，根据本发明，可以将纳米管阵列电连接到宏观半导体电子器件。此外，根据本发明的纳米管阵列可以在衬底和催化剂层之间具有电绝缘层。该电绝缘层优选地具有使得至少一个纳米管在其端部部分处于电绝缘层上并且在其中心部分未被覆盖的形貌。由于至少一个纳米管的表面部分未被覆盖，纳米管的未被覆盖的表面可以用作主动传感器表面。例如，纳米管的未覆盖表面可以与围绕纳米管阵列的气氛进行操作接触。在某些气体的存在下，纳米管的电阻显着变化。因此，由于纳米管是透明和未覆盖的，所以纳米管阵列可用于许多传感器应用中。

13. 发明授权

US08124475B2 Integrated circuit arrangement with capacitor and fabrication method 有权
标题翻译：具有电容器的集成电路布置及其制造方法
公开(公告)号：US08124475B2
公开(公告)日：2012-02-28
申请号：US12414120
申请日：2009-03-30
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。

14. 发明授权

US06320447B1 Circuit configuration with single-electron components, and operating method 有权
标题翻译：具有单电子元件的电路配置和操作方法
公开(公告)号：US06320447B1
公开(公告)日：2001-11-20
申请号：US09707032
申请日：2000-11-06
申请人： Wolfgang Rösner , Ties Ramcke , Lothar Risch
发明人： Wolfgang Rösner , Ties Ramcke , Lothar Risch
IPC分类号： H03K1762
CPC分类号： G06F7/527 , B82Y10/00 , G06F7/502 , G06F7/505 , G06F2207/4828 , H03K19/08 , Y10S977/936 , Y10S977/937 , Y10S977/94
摘要： The circuit configuration has at least five single-electron transistors, three of which are connected via a second main node and a third main node between a first main node and an output. The fourth single-electron transistor is connected between the second main node and a first supply voltage, with its gate electrode being connected to the first main node. The fifth single-electron transistor is connected between the third main node and the first supply voltage, with its gate electrode being connected to the second main node. The circuit configuration is suitable for use as a full adder and as a multiplier.
摘要翻译：电路配置具有至少五个单电子晶体管，其中三个通过第二主节点和第一主节点与输出端之间的第三主节点连接。第四单电子晶体管连接在第二主节点和第一电源电压之间，其栅电极连接到第一主节点。第五单电晶体管连接在第三主节点和第一电源电压之间，其栅电极连接到第二主节点。电路配置适合用作全加器和乘法器。

15. 发明授权

US06909141B2 Method for producing a vertical semiconductor transistor component and vertical semiconductor transistor component 失效
标题翻译：用于制造垂直半导体晶体管部件和垂直半导体晶体管部件的方法
公开(公告)号：US06909141B2
公开(公告)日：2005-06-21
申请号：US10047013
申请日：2002-01-16
申请人： Wolfgang Rösner , Thomas Schulz , Lothar Risch , Thomas Äugle , Herbert Schäfer , Martin Franosch
发明人： Wolfgang Rösner , Thomas Schulz , Lothar Risch , Thomas Äugle , Herbert Schäfer , Martin Franosch
IPC分类号： H01L21/335 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/76 , H01L51/00 , H01L51/05 , H01L51/30 , H01L21/8238
CPC分类号： B82Y10/00 , H01L21/823487 , H01L27/088 , H01L29/66439 , H01L29/66666 , H01L29/7613 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.
摘要翻译：通过使用统计掩模在衬底上构建垂直半导体晶体管组件。垂直半导体晶体管组件具有统计分布在衬底上的垂直柱结构。垂直柱结构在其基极侧电连接到第一公共电接触。垂直柱结构沿垂直方向包括不同导电性的层区，并且在其周壁上具有绝缘层。导电材料沉积在柱结构之间并形成半导体晶体管组件的第二电接触。支柱结构在其封盖侧与第三公共电触头电接触。

16. 发明授权

US06614069B2 Nonvolatile semiconductor memory cell and method for fabricating the memory cell 有权
公开(公告)号：US06614069B2
公开(公告)日：2003-09-02
申请号：US10054440
申请日：2002-01-22
申请人： Wolfgang Rösner , Thomas Schulz , Lothar Risch , Ties Ramcke
发明人： Wolfgang Rösner , Thomas Schulz , Lothar Risch , Ties Ramcke
IPC分类号： H01L29788
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/7887 , H01L29/7888
摘要： A nonvolatile semiconductor memory cell includes a transistor component formed on a substrate and a storage node that determines the switching state of the transistor component. The storage node is arranged near a control gate electrode. The storage node has a group of vertically oriented column structures having at least two semiconductor layer zones and an insulating layer zone situated between the two semiconductor layer zones.

17. 发明授权

US06864129B2 Double gate MOSFET transistor and method for the production thereof 失效
标题翻译：双栅极MOSFET晶体管及其制造方法
公开(公告)号：US06864129B2
公开(公告)日：2005-03-08
申请号：US09996279
申请日：2001-11-28
申请人： Lothar Risch , Wolfgang Rösner , Thomas Schulz
发明人： Lothar Risch , Wolfgang Rösner , Thomas Schulz
IPC分类号： H01L29/417 , H01L21/20 , H01L21/336 , H01L29/786 , H01L21/00 , H01L27/01
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed is embedded in a spacer material and contact-connected by source and drain regions which are filled into depressions that are etched on opposite sides of the semiconductor layer structure. Afterwards, the spacer material is etched out selectively and replaced by the electrically conductive gate electrode material.
摘要翻译：描述双栅极MOSFET晶体管及其制造方法。在这种情况下，要形成的晶体管沟道的半导体层结构被嵌入到间隔物材料中，并且被源极和漏极区域接触，其被填充到在半导体层结构的相对侧被蚀刻的凹陷中。之后，间隔材料被选择性蚀刻掉，并由导电栅电极材料代替。

18. 发明授权

US06490190B1 Memory cell configuration, magnetic ram, and associative memory 有权
标题翻译：存储单元配置，磁力柱和关联存储器
公开(公告)号：US06490190B1
公开(公告)日：2002-12-03
申请号：US09528159
申请日：2000-03-17
申请人： Ties Ramcke , Wolfgang Rösner , Lothar Risch
发明人： Ties Ramcke , Wolfgang Rösner , Lothar Risch
IPC分类号： G11C1100
CPC分类号： G11C11/16 , G11C15/02 , G11C15/046
摘要： A memory cell configuration has word lines and bit lines that extend transversely with respect thereto. Memory elements with a giant magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The bit lines are each connected to a sense amplifier by means of which the potential on the respective bit line can be regulated to a reference potential and at which an output signal can be picked off. The memory cell configuration can be used both as an MRAM and as an associative memory.
摘要翻译：存储单元配置具有相对于其横向延伸的字线和位线。具有巨磁阻效应的存储元件分别连接在一条字线和一条位线之间。位线各自连接到读出放大器，通过该读出放大器可以将相应位线上的电位调节到参考电位，并且可以在其上拾取输出信号。存储单元配置可以用作MRAM和关联存储器。

19. 发明授权

US06337247B1 Method of producing a vertical MOS transistor 有权
标题翻译：制造垂直MOS晶体管的方法
公开(公告)号：US06337247B1
公开(公告)日：2002-01-08
申请号：US09487411
申请日：2000-01-18
申请人： Thomas Schulz , Thomas Äugle , Wolfgang Rösner , Lothar Risch
发明人： Thomas Schulz , Thomas Äugle , Wolfgang Rösner , Lothar Risch
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/7827 , H01L29/7834
摘要： A spacer is used as a mask in an etching step during which a layer structure is produced for a channel layer and for a first source/drain region. After the layer structure has been produced, the first source/drain region and a second source/drain region can be produced by implantation. The second source/drain region is self-aligned on two mutually opposite flanks of the layer structure. A gate electrode can be produced in the form of a spacer on the two flanks. In order to avoid a capacitance formed by a first contact of the gate electrode and the first source/drain region, a part of the first source/drain region may be removed. If the layer structure is produced along edges of an inner area, then a third contact of the second source/drain region may be produced inside the inner area in order to reduce the surface area of the transistor.
摘要翻译：在蚀刻步骤中使用间隔物作为掩模，在该步骤中，为沟道层和第一源极/漏极区域产生层结构。在生成层结构之后，可以通过注入产生第一源极/漏极区域和第二源极/漏极区域。第二源极/漏极区域在层结构的两个相互相对的侧面上自对准。可以在两个侧面上以间隔物的形式制造栅电极。为了避免由栅极电极和第一源极/漏极区域的第一接触形成的电容，可以去除第一源极/漏极区域的一部分。如果沿着内部区域的边缘产生层结构，则可以在内部区域内产生第二源极/漏极区域的第三接触，以便减小晶体管的表面积。

20. 发明授权

US07291877B2 Integrated circuit arrangement with capacitor 有权
标题翻译：集成电路布置与电容器
公开(公告)号：US07291877B2
公开(公告)日：2007-11-06
申请号：US10529990
申请日：2003-10-10
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。厚的绝缘区域比控制电极绝缘区域厚。控制电极含有与远电极区域相同的材料。

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