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1. 发明公开

EP1010205A2 SCHALTUNGSANORDNUNG MIT EINZELELEKTRON-BAUELEMENTEN, VERFAHREN ZU DEREN BETRIEB UND ANWENDUNG DES VERFAHRENS ZUR ADDITION VON BINÄRZAHLEN 有权
标题翻译：电路各个电子部件，操作方法有关步骤的加法二进制数的应用
公开(公告)号：EP1010205A2
公开(公告)日：2000-06-21
申请号：EP98952513.4
申请日：1998-08-26
申请人： Infineon Technologies AG
发明人： RÖSNER, Wolfgang , RAMCKE, Ties , RISCH, Lothar
IPC分类号： H01L29/76
CPC分类号： G06F7/505 , G06F7/502 , G06F2207/4828 , H03K19/02 , Y10S977/89 , Y10S977/937 , Y10S977/94
摘要： A circuit arrangement with lone-electron components has at least one lone-electron transistor, which is placed between a first main node and a second main node. The first node is capacitive betweeen a first operating voltage tap and a second operating voltage tap. The gate electrode of the lone-electron transistor is connected to a control voltage tap. The circuit arrangement concerned is suited for the logical combination of binary numbers, the positions of which are recorded in the first and second main nodes.

2. 发明申请

WO99057813A1 CIRCUIT WITH INDIVIDUAL ELECTRON COMPONENTS AND METHOD FOR THE OPERATION THEREOF 审中-公开
标题翻译：个别电子组件的电路和方法操作
公开(公告)号：WO99057813A1
公开(公告)日：1999-11-11
申请号：PCT/DE1999/000715
申请日：1999-03-15
IPC分类号： G06F7/50 , G06F7/52 , H01L29/66 , H03K19/08
CPC分类号： G06F7/527 , B82Y10/00 , G06F7/502 , G06F7/505 , G06F2207/4828 , H03K19/08 , Y10S977/936 , Y10S977/937 , Y10S977/94
摘要： A circuit with at least five individual electron transistors, whereby three of said transistors (ET1, ET2, ET3) are mounted between a first main node (H1) and an output (A) via a second main node (H2) and a third main node (H3). The fourth individual electron transistor (ET4) is mounted between the second main node and a first supply voltage (V1), whereby the gate electrode pertaining thereto (G4) is connected to the first main node (H1). The fifth individual electron transistor (ET5) is mounted between the third main node (H3) and the first supply voltage (VI), whereby the gate electrode (G5) pertaining thereto is connected to the second main node (H2). The circuit is suitable for use as a full loader and a multiplier.
摘要翻译：一种电路装置，具有通过第二主节点（H2）和第一主节点（H1）和一个输出（A）之间的第三主节点（H3）至少五个单电子晶体管，其中三个（ET1，ET2，ET3）连接。第四单电子晶体管（ET4）连接在第二主节点和第一电源电压（V1）之间，其栅极电极（G4）与第一主节点（H1）和第五单电子晶体管（ET5）是之间的第三主节点（H3）和该第一电源电压切换（V1），其栅极电极连接到（G5）到第二Hautpknoten（H2）。该电路装置适合作为全加法器和乘法器。

3. 发明申请

WO99012212A2 LONE-ELECTRON CIRCUIT ARRANGEMENT, OPERATING MODE, AND APPLICATION FOR ADDING BINARY NUMBERS 审中-公开
标题翻译：电路各个电子部件，操作方法有关步骤的加法二进制数的应用
公开(公告)号：WO99012212A2
公开(公告)日：1999-03-11
申请号：PCT/DE1998/002521
申请日：1998-08-26
IPC分类号： G06F7/501 , G06F7/50 , G06F7/505 , H01L29/66 , H03K17/00 , H03K19/02 , H01L29/76
CPC分类号： G06F7/505 , G06F7/502 , G06F2207/4828 , H03K19/02 , Y10S977/89 , Y10S977/937 , Y10S977/94
摘要： A circuit arrangement with lone-electron components has at least one lone-electron transistor, which is placed between a first main node and a second main node. The first node is capacitive betweeen a first operating voltage tap and a second operating voltage tap. The gate electrode of the lone-electron transistor is connected to a control voltage tap. The circuit arrangement concerned is suited for the logical combination of binary numbers, the positions of which are recorded in the first and second main nodes.
摘要翻译：在具有单电子部件的电路布置中，至少一个单电子晶体管，其连接第一主节点和第二主节点之间。第一主节点是第一电源电压端子和第二操作电压端子之间连接的电容。单电子晶体管的栅电极被连接到控制电压端子。该电路装置适合于二进制数，其数字被存储在第一和第二主节点的逻辑连接。

4. 发明申请

WO9912212A3 LONE-ELECTRON CIRCUIT ARRANGEMENT, OPERATING MODE, AND APPLICATION FOR ADDING BINARY NUMBERS 审中-公开
标题翻译：单一电子元件的电路布置，操作和应用二元数字加法方法
公开(公告)号：WO9912212A3
公开(公告)日：1999-06-03
申请号：PCT/DE9802521
申请日：1998-08-26
申请人： SIEMENS AG , ROESNER WOLFGANG , RAMCKE TIES , RISCH LOTHAR
发明人： ROESNER WOLFGANG , RAMCKE TIES , RISCH LOTHAR
IPC分类号： G06F7/501 , G06F7/50 , G06F7/505 , H01L29/66 , H03K17/00 , H03K19/02 , H03K19/21
CPC分类号： G06F7/505 , G06F7/502 , G06F2207/4828 , H03K19/02 , Y10S977/89 , Y10S977/937 , Y10S977/94
摘要： A circuit arrangement with lone-electron components has at least one lone-electron transistor, which is placed between a first main node and a second main node. The first node is capacitive betweeen a first operating voltage tap and a second operating voltage tap. The gate electrode of the lone-electron transistor is connected to a control voltage tap. The circuit arrangement concerned is suited for the logical combination of binary numbers, the positions of which are recorded in the first and second main nodes.
摘要翻译：在具有单电子部件的电路装置中，提供至少一个单电子晶体管，其连接在第一主节点和第二主节点之间。第一主节点电容性地连接在第一工作电压端子和第二工作电压端子之间。单电子晶体管的栅极连接到控制电压端子。该电路装置适用于其位置存储在第一和第二主节点中的二进制数的逻辑组合。

5. 发明授权

EP1078461B1 SCHALTUNGSANORDNUNG MIT EINZELELEKTRON-BAUELEMENTEN UND VERFAHREN ZU DEREN BETRIEB 有权
标题翻译：个别电子组件的电路和方法操作
公开(公告)号：EP1078461B1
公开(公告)日：2002-09-18
申请号：EP99919077.0
申请日：1999-03-15
申请人： Infineon Technologies AG
发明人： RÖSNER, Wolfgang , RAMCKE, Ties , RISCH, Lothar
IPC分类号： H03K19/08
CPC分类号： G06F7/527 , B82Y10/00 , G06F7/502 , G06F7/505 , G06F2207/4828 , H03K19/08 , Y10S977/936 , Y10S977/937 , Y10S977/94
摘要： A circuit with at least five individual electron transistors, whereby three of said transistors (ET1, ET2, ET3) are mounted between a first main node (H1) and an output (A) via a second main node (H2) and a third main node (H3). The fourth individual electron transistor (ET4) is mounted between the second main node and a first supply voltage (V1), whereby the gate electrode pertaining thereto (G4) is connected to the first main node (H1). The fifth individual electron transistor (ET5) is mounted between the third main node (H3) and the first supply voltage (VI), whereby the gate electrode (G5) pertaining thereto is connected to the second main node (H2). The circuit is suitable for use as a full loader and a multiplier.

6. 发明公开

EP0644480A2 Multiple resonant tunneling circuits for positive digit multi-valued logic operations 失效
标题翻译：电路中使用，用于与正数多值逻辑操作的多个共振隧道效应。
公开(公告)号：EP0644480A2
公开(公告)日：1995-03-22
申请号：EP94303702.8
申请日：1994-05-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Taddiken, Albert H.
IPC分类号： G06F7/49 , H03K23/00 , H01L29/73
CPC分类号： B82Y10/00 , G06F7/49 , G06F2207/4828
摘要： Multiple resonant tunneling devices offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. A multivalued logic adder is disclosed, wherein two numbers represented by positive digit base-M range-N words are added by two-input summation circuits (40) which sum corresponding digits, then the digit sums are decomposed into a binary representation by range-7 multivalued to binary converter circuits (42) , then three-input summation circuits (44) sum appropriate bits of the binary representations to calculate the digits of a positive digit base-2 range-4 word whose value is the sum of the two numbers. Preferably, the decomposition to binary representation is performed by multi-valued folding circuits (56) which are connected by voltage divider circuitry. Preferably, the multi-valued folding circuits contain multiple-peak resonant tunneling transistors (54) . Ripple carries are eliminated and the speed of the adder is independent of input word width.
摘要翻译：多个谐振隧穿器件为实现超高密度，超高性能多值逻辑运算的集成电路显著优点。多值逻辑加法器盘游离缺失，worin由正数字基-M范围-N字表示两个数字由两输入求和电路40，其总和CORRESPONDING位数，那么数字总和按范围-7多值分解成二进制表示被添加二进制转换器电路42，然后三输入求和电路的二进制表示的44个适当总和比特来计算正数字基-2-范围-4字，其值是两个数字的总和的数字。优选地，所述分解到二进制表示通过由分压器电路连接的多值折叠电路56执行的。优选地，该多值折叠电路包含多峰共振隧穿晶体管54纹波携带被消除并且加法器的速度是独立于输入字的宽度。

7. 发明授权

US4982356A Multiple-valued current mode adder implemented by transistor having negative transconductance 失效
标题翻译：由具有负跨导的晶体管实现的多值电流模式加法器
公开(公告)号：US4982356A
公开(公告)日：1991-01-01
申请号：US313485
申请日：1989-02-22
申请人： Yuji Ando
发明人： Yuji Ando
IPC分类号： G06F7/501 , G06F7/49 , G06F7/503 , G06F7/508 , G06G7/14 , H03K19/10
CPC分类号： B82Y10/00 , G06F7/49 , G06F2207/4828
摘要： A multiple-valued current-mode adder has a current-to-voltage converter for converting a total current into an input voltage level, the total current comprising current values respectively representative of the values of input integers a transistor with a negative transconductance due to a resonant tunneling phenomenon and a threshold value detecting circuit with an output current which changes from a first level to a second level. The transistor and the threshold value detecting circuit have respective input nodes supplied with the input voltage level for respectively producing output currents respectively representative of a sum and a carry in accordance with the input voltage level.
摘要翻译：多值电流模式加法器具有电流 - 电压转换器，用于将总电流转换为输入电压电平，所述总电流包括分别代表输入整数值的电流值，具有负跨导的晶体管由于谐振隧道现象和具有从第一电平变化到第二电平的输出电流的阈值检测电路。晶体管和阈值检测电路具有被提供有输入电压电平的各个输入节点，用于分别产生分别表示根据输入电压电平的和和进位的输出电流。

8. 发明授权

US3253133A Threshold circuits 失效
标题翻译：阈值电路
公开(公告)号：US3253133A
公开(公告)日：1966-05-24
申请号：US18847562
申请日：1962-04-18
申请人： RCA CORP
发明人： BENJAMIN RABINOVICI , RENTON CHARLES A
IPC分类号： G06F7/50 , G06F7/501 , H03K19/08
CPC分类号： G06F7/5013 , G06F2207/4818 , G06F2207/4828 , H03K19/0813

9. 发明授权

US3248529A Full adder 失效
公开(公告)号：US3248529A
公开(公告)日：1966-04-26
申请号：US19100962
申请日：1962-04-30
申请人： IBM
发明人： BUELOW FRED K , MANFRED HILSENRATH
IPC分类号： G06F7/50 , G06F7/501 , H03K19/082 , H03K19/086
CPC分类号： G06F7/5013 , G06F2207/4818 , G06F2207/4828 , H03K19/082 , H03K19/086

10. 发明授权

US3177376A Semiconductor logic circuit comprising tunnel diodes and backward diodes 失效
标题翻译：半导体逻辑电路包括隧道二极管和反向二极管
公开(公告)号：US3177376A
公开(公告)日：1965-04-06
申请号：US12452561
申请日：1961-07-17
申请人： IBM
发明人： WOLTERMAN ARDEN J
IPC分类号： G06F7/50 , G06F7/502 , H03K19/10
CPC分类号： G06F7/502 , G06F2207/4828 , H03K19/10

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