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11. 发明授权

US08427796B2 High voltage, high frequency ESD protection circuit for RF ICs 有权
标题翻译： RF IC的高压，高频ESD保护电路
公开(公告)号：US08427796B2
公开(公告)日：2013-04-23
申请号：US12748067
申请日：2010-03-26
申请人： Eugene R. Worley , ByungWook Min , Der-woei Wu
发明人： Eugene R. Worley , ByungWook Min , Der-woei Wu
IPC分类号： H02H9/00
CPC分类号： H03F1/52 , H01L27/0274
摘要： Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse. Alternate embodiments further reduce the capacitance of the ESD protection circuit by using only a positive ESD clamp to provide ESD protection during a positive ESD pulse while protection for a negative ESD pulse is provided by a discharge path formed by a path of an RF front-end switch coupled to a negative ESD diode.
摘要翻译：描述了需要高压和高频操作的RFIC的改进的ESD保护电路。与预充电电路和二极管网络相结合的共源共栅接地栅极复位NFET（GGNFET）导致具有低电容和高导通电压的正ESD保护钳位。正电压ESD保护钳在正电压ESD脉冲期间为IC提供ESD保护。公开了一种负ESD保护钳的示例性实施例，其中使用偏置电路或电荷泵代替预充电电路，以允许偏置电路或电荷泵与二极管网络和共源共栅接地的组合门复位NFET，以提供防止负ESD电压脉冲的保护。在正或负电压ESD脉冲期间，正和负ESD保护钳的组合可为IC提供ESD保护。替代实施例通过仅使用正的ESD钳位来在正的ESD脉冲期间提供ESD保护来进一步减小ESD保护电路的电容，同时通过由RF前端的路径形成的放电路径来提供负的ESD脉冲的保护开关耦合到负ESD二极管。

12. 发明申请

US20120074496A1 Diode Having A Pocket Implant Blocked And Circuits And Methods Employing Same 有权
标题翻译：具有口袋植入物阻塞的二极管和使用相同的电路和方法
公开(公告)号：US20120074496A1
公开(公告)日：2012-03-29
申请号：US13075701
申请日：2011-03-30
申请人： Reza Jalilizeinali , Eugene R. Worley , Evan Siansuri , Sreeker Dundigal
发明人： Reza Jalilizeinali , Eugene R. Worley , Evan Siansuri , Sreeker Dundigal
IPC分类号： H01L23/62 , B05C11/00 , H01L21/762 , H01L29/78 , H01L29/861
CPC分类号： H01L29/66356 , H01L27/0255 , H01L29/0649 , H01L29/6609 , H01L29/7391 , H01L29/861 , H01L2924/0002 , H04B1/109 , H04B1/48 , H01L2924/00
摘要： Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance.
摘要翻译：提供包括门控二极管和浅沟槽隔离（STI）二极管，制造方法和相关电路的二极管，而不需要至少一个卤素或口袋注入，从而减小二极管的电容。以这种方式，二极管可以用于对负载电容具有敏感性的电路和其它器件，同时仍然获得二极管的性能特性。栅极二极管的这种特性包括快速接通时间和高电导，使得门极二极管非常适合于静电放电（ESD）保护电路。二极管包括具有阱区和其上的绝缘层的半导体衬底。在绝缘层上形成栅电极。阳极和阴极区域设置在阱区中。形成P-N结。在二极管中阻塞至少一个口袋植入物以减少电容。

13. 发明申请

US20100232077A1 GATED DIODE HAVING AT LEAST ONE LIGHTLY-DOPED DRAIN (LDD) IMPLANT BLOCKED AND CIRCUITS AND METHODS EMPLOYING SAME 失效
标题翻译：具有至少一个轻型排水（LDD）的嵌入式二极管嵌入式阻塞和电路及其使用方法
公开(公告)号：US20100232077A1
公开(公告)日：2010-09-16
申请号：US12403418
申请日：2009-03-13
申请人： Eugene R. Worley
发明人： Eugene R. Worley
IPC分类号： H02H9/04 , H01L21/336 , H01L29/78
CPC分类号： H04B1/48 , H01L27/0255 , H01L29/66356 , H01L29/7391 , H01L2924/0002 , H01L2924/00
摘要： Gated diodes, manufacturing methods, and related circuits are provided wherein at least one lightly-doped drain (LDD) implant is blocked in the gated diode to reduce its capacitance. In this manner, the gated diode may be used in circuits and other applications whose performance is sensitive to load capacitance while still obtaining the performance characteristics of a gated diode. These characteristics include fast turn-on times and high conductance, making the gated diodes disclosed herein well-suited for electro-static discharge (ESD) protection circuits as one application example. The examples of the gated diode disclosed herein include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region, wherein a P-N junction is formed. At least one LDD implant is blocked in the gated diode to reduce capacitance.
摘要翻译：提供了栅极二极管，制造方法和相关电路，其中至少一个轻掺杂漏极（LDD）注入在门控二极管中被阻塞以降低其电容。以这种方式，门控二极管可以用于电路和其他对负载电容敏感的应用，同时仍然获得门控二极管的性能特性。这些特性包括快速接通时间和高电导性，使得本文公开的门控二极管非常适合作为一个应用示例的静电放电（ESD）保护电路。本文公开的门控二极管的示例包括具有阱区和其上的绝缘层的半导体衬底。在绝缘层上形成栅电极。阳极和阴极区域设置在阱区中，其中形成P-N结。在栅极二极管中至少有一个LDD注入被阻塞以降低电容。

14. 发明授权

US5784190A Electro-micro-mechanical shutters on transparent substrates 失效
标题翻译：透明基板上的电 - 微机械百叶窗
公开(公告)号：US5784190A
公开(公告)日：1998-07-21
申请号：US429674
申请日：1995-04-27
申请人： Eugene R. Worley
发明人： Eugene R. Worley
IPC分类号： G02B26/02 , G02B26/00
CPC分类号： G02B26/02
摘要： Micro-mechanical flappers for use as an electronic display technology and methods related to the fabrication thereof are disclosed. These methods are consistent with standard silicon based semiconductor processing used to make integrated circuits. One embodiment shows how cross-talk or flapper-to-flapper interference is minimized using a Digital Signal Processor (DSP) to compensate for this undesirable effect. Also disclosed is the construction of a micro-mechanical flapper that uses a combination of two springs, viz. a leaf spring and a torsion spring, to reduce maximum bending stress and to lower operating voltage. Also, the spring construction is made such that axial stability is improved over a single leaf spring approach and a light shield is integrated onto the flapper assembly so that the overhead stationary electrode is simply a supporting glass plate with a transparent conducting layer over its surface. Another construction is also disclosed in which the flapper and light shield are integrated onto the overhead electrode assembly while the attracting stationary counter electrode, select transistor, and retention capacitor are located on another integrated assembly. Finally, an L-shaped attracting electrode is used to lower voltages required to bend the flapper spring.
摘要翻译：公开了用作电子显示技术的微机械襟翼和与其制造相关的方法。这些方法与用于制造集成电路的标准硅基半导体处理一致。一个实施例示出了如何使用数字信号处理器（DSP）来弥补这种不希望有的影响的串扰或挡板对挡板的干扰。还公开了使用两个弹簧的组合的微机械挡板的构造，即，板簧和扭簧，以减少最大弯曲应力和降低工作电压。此外，弹簧结构被制成使得通过单个板簧方式提高了轴向稳定性，并且遮光板集成在挡板组件上，使得顶置固定电极仅仅是在其表面上具有透明导电层的支撑玻璃板。还公开了另一种结构，其中挡板和遮光罩集成在顶置电极组件上，而吸引静止对电极，选择晶体管和保持电容器位于另一个集成组件上。最后，使用L形吸引电极来降低弯曲挡板弹簧所需的电压。

15. 发明授权

US5466948A Monolithic silicon opto-coupler using enhanced silicon based LEDS 失效
标题翻译：使用增强型硅基LED的单片硅光耦合器
公开(公告)号：US5466948A
公开(公告)日：1995-11-14
申请号：US320232
申请日：1994-10-11
申请人： Eugene R. Worley
发明人： Eugene R. Worley
IPC分类号： H01L31/173 , H01L31/12 , H01L31/16
CPC分类号： H01L31/173
摘要： A monolithic opto-coupler employing silicon-insulator technology in which at least two p-type silicon islands disposed on said insulating layer and a light emitting diode having enhanced light emitting efficiency is formed on one of said islands. The enhanced light emitting diode is either of the type having the surface of said p-type silicon island being electrochemically etched to provide a porous silicon layer, having carbon implanted in damaged silicon, or having an amorphous silicon-carbide layer. A silicon diode detector is formed on the other island(s) and a reflective layer is disposed over the light-emitting diode and the detectors for coupling light generated in the light emitting diode to the silicon diode detector.
摘要翻译：一种使用硅绝缘体技术的单片光耦合器，其中在所述岛之一上形成有设置在所述绝缘层上的至少两个p型硅岛和具有增强的发光效率的发光二极管。增强发光二极管是具有所述p型硅岛的表面的类型之一，被电化学蚀刻以提供多孔硅层，其中碳被注入损坏的硅中，或具有非晶碳化硅层。硅二极管检测器形成在另一个岛上，并且反射层设置在发光二极管上方，检测器用于将在发光二极管中产生的光耦合到硅二极管检测器。

16. 发明授权

US5017811A CMOS TTL input buffer using a ratioed inverter with a threshold voltage adjusted N channel field effect transistor 失效
标题翻译： CMOS TTL输入缓冲器采用具有阈值电压调节的N沟道场效应晶体管的比例逆变器
公开(公告)号：US5017811A
公开(公告)日：1991-05-21
申请号：US427383
申请日：1989-10-27
申请人： Eugene R. Worley
发明人： Eugene R. Worley
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/018521 , H03K19/00384 , H03K19/0948
摘要： The invention applies a weak forward bias to the body of the NFET transistor of a PFET-NFET TTL inverter buffer circuit to lower the NFET threshold voltage by about 0.45 volts, as a result of 1.5.mu. amps of body-source current providing a body to source voltage of about 0.5 volts to achieve a near ideal switch point of 1.45 volts under nominal conditions. Also a modified inverter circuit with biasing source, two diodes for trip voltage of 1.4 volts and a comparator constitute a central bias generator for supplying proper bias to the body of the NFETs of a plurality of TTL input buffers.
摘要翻译：本发明将PFET-NFET TTL反相器缓冲电路的NFET晶体管的主体施加弱的正向偏压，以将NFET阈值电压降低大约0.45伏特，这是由于1.5μA的体电源电流提供了一个主体源电压约为0.5伏特，在标称条件下达到1.45伏特的接近理想开关点。还有一种具有偏置源的修正的反相器电路，用于1.4伏的跳闸电压的两个二极管和一个比较器构成了用于向多个TTL输入缓冲器的NFET的主体提供适当偏置的中心偏置发生器。

17. 发明授权

US08536893B2 Circuit for measuring magnitude of electrostatic discharge (ESD) events for semiconductor chip bonding 有权
标题翻译：用于测量半导体芯片接合的静电放电（ESD）事件的电平的电路
公开(公告)号：US08536893B2
公开(公告)日：2013-09-17
申请号：US12577780
申请日：2009-10-13
申请人： Eugene R. Worley , Brian Matthew Henderson
发明人： Eugene R. Worley , Brian Matthew Henderson
IPC分类号： G01R31/02
CPC分类号： G01R31/002 , H01L22/34 , H01L2224/16225
摘要： A circuit for recording a magnitude of an ESD event during semiconductor assembly includes a voltage divider connected between an input and a ground. The circuit also includes a measurement block having a recorder device. Each measurement block receives current from a segment of the voltage divider. The magnitude of the ESD event is determined based upon a read-out of the measurement devices after the ESD event. The recorder device may be a capacitor that would be damaged during the ESD event. During the ESD event the capacitor may be damaged. Reading out the recorder device determines if the magnitude of the ESD event exceeded a threshold magnitude that damages the capacitor.
摘要翻译：用于在半导体组件期间记录ESD事件的大小的电路包括连接在输入和地之间的分压器。电路还包括具有记录器装置的测量块。每个测量块从分压器的一个段接收电流。基于在ESD事件之后读出测量装置来确定ESD事件的大小。记录器装置可以是在ESD事件期间被损坏的电容器。在ESD事件期间，电容可能会损坏。读出记录器装置确定ESD事件的大小是否超过损坏电容器的阈值大小。

18. 发明授权

US08531806B2 Distributed building blocks of R-C clamping circuitry in semiconductor die core area 有权
标题翻译：半导体芯片区域中R-C钳位电路的分布式构建块
公开(公告)号：US08531806B2
公开(公告)日：2013-09-10
申请号：US13173977
申请日：2011-06-30
申请人： Reza Jalilizeinali , Evan Siansuri , Sreeker R. Dundigal , Eugene R. Worley
发明人： Reza Jalilizeinali , Evan Siansuri , Sreeker R. Dundigal , Eugene R. Worley
IPC分类号： H02H3/22
CPC分类号： H01L27/0285 , H01L27/0296 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes resistor-capacitor (RC) clamping circuitry for electrostatic discharge (ESD) protection of the semiconductor die. The RC clamping circuitry includes building blocks distributed in the pad ring and in the core area of the semiconductor die. The building blocks include at least one capacitor block in the core area. The RC clamping circuitry also includes chip level conductive layer connections between each of the distributed building blocks.
摘要翻译：半导体管芯包括用于半导体管芯的静电放电（ESD）保护的电阻 - 电容（RC）钳位电路。 RC钳位电路包括分布在焊盘环和半导体管芯的芯区域中的构建块。构建块包括核心区域中的至少一个电容器块。 RC钳位电路还包括每个分布式构建块之间的芯片级导电层连接。

19. 发明申请

US20110176245A1 HIGH VOLTAGE, HIGH FREQUENCY ESD PROTECTION CIRCUIT FOR RF ICs 有权
标题翻译：用于RF IC的高电压，高频ESD保护电路
公开(公告)号：US20110176245A1
公开(公告)日：2011-07-21
申请号：US12748067
申请日：2010-03-26
申请人： Eugene R. Worley , ByungWook Min , Der-woei Wu
发明人： Eugene R. Worley , ByungWook Min , Der-woei Wu
IPC分类号： H02H9/00
CPC分类号： H03F1/52 , H01L27/0274
摘要： Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse. Alternate embodiments further reduce the capacitance of the ESD protection circuit by using only a positive ESD clamp to provide ESD protection during a positive ESD pulse while protection for a negative ESD pulse is provided by a discharge path formed by a path of an RF front-end switch coupled to a negative ESD diode.
摘要翻译：描述了需要高压和高频操作的RFIC的改进的ESD保护电路。与预充电电路和二极管网络相结合的共源共栅接地栅极复位NFET（GGNFET）导致具有低电容和高导通电压的正ESD保护钳位。正电压ESD保护钳在正电压ESD脉冲期间为IC提供ESD保护。公开了一种负ESD保护钳的示例性实施例，其中使用偏置电路或电荷泵代替预充电电路，以允许偏置电路或电荷泵与二极管网络和共源共栅接地的组合门复位NFET，以提供防止负ESD电压脉冲的保护。在正或负电压ESD脉冲期间，正和负ESD保护钳的组合可为IC提供ESD保护。替代实施例通过仅使用正的ESD钳位来在正的ESD脉冲期间提供ESD保护来进一步减小ESD保护电路的电容，同时通过由RF前端的路径形成的放电路径来提供负的ESD脉冲的保护开关耦合到负ESD二极管。

20. 发明申请

US20110084362A1 Active Diode Having No Gate and No Shallow Trench Isolation 有权
标题翻译：没有门的活性二极管和没有浅沟槽隔离
公开(公告)号：US20110084362A1
公开(公告)日：2011-04-14
申请号：US12751903
申请日：2010-03-31
申请人： Reza Jalilizeinali , Eugene R. Worley , Evan Siansuri , Sreeker R. Dundigal
发明人： Reza Jalilizeinali , Eugene R. Worley , Evan Siansuri , Sreeker R. Dundigal
IPC分类号： H01L29/861 , H01L21/762
CPC分类号： H01L29/8611 , H01L29/0692 , H01L29/66128
摘要： An active diode with fast turn-on time, low capacitance, and low turn-on resistance may be manufactured without a gate and without a shallow trench isolation region between doped regions of the diode. A short conduction path in the active diode allows a fast turn-on time, and a lack of gate oxide reduces susceptibility of the active diode to extreme voltages. The active diode may be implemented in integrated circuits to prevent and reduce damage from electrostatic discharge (ESD) events. Manufacturing the active diode is accomplished by depositing a salicide block between doped regions of the diode before salicidation. After the salicide layers are formed on the doped regions, the salicide block is removed.
摘要翻译：可以在没有栅极并且在二极管的掺杂区域之间没有浅沟槽隔离区域的情况下制造具有快导通时间，低电容和低导通电阻的有源二极管。有源二极管中的短导通路径允许快速导通时间，并且缺少栅极氧化物降低有源二极管对极端电压的敏感性。有源二极管可以在集成电路中实现，以防止和减少静电放电（ESD）事件的损坏。有源二极管的制造是通过在盐析之前在二极管的掺杂区域之间沉积自对准硅化物块来实现的。在掺杂区域上形成自对准硅化物层之后，去除硅化物块。

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