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1. 发明申请

US20120224284A1 DISTRIBUTED BUILDING BLOCKS OF R-C CLAMPING CIRCUITRY IN SEMICONDUCTOR DIE CORE AREA 有权
标题翻译：半导体芯片领域的R-C钳位电路分布式建筑块
公开(公告)号：US20120224284A1
公开(公告)日：2012-09-06
申请号：US13173977
申请日：2011-06-30
申请人： Reza Jalilizeinali , Evan Siansuri , Sreeker R. Dundigal , Eugene R. Worley
发明人： Reza Jalilizeinali , Evan Siansuri , Sreeker R. Dundigal , Eugene R. Worley
IPC分类号： H02H9/04 , H05K3/30
CPC分类号： H01L27/0285 , H01L27/0296 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes resistor-capacitor (RC) clamping circuitry for electrostatic discharge (ESD) protection of the semiconductor die. The RC clamping circuitry includes building blocks distributed in the pad ring and in the core area of the semiconductor die, The building blocks include at least one capacitor block in the core area, The RC clamping circuitry also includes chip level conductive layer connections between each of the distributed building blocks.
摘要翻译：半导体管芯包括用于半导体管芯的静电放电（ESD）保护的电阻 - 电容（RC）钳位电路。 RC钳位电路包括分布在焊盘环和半导体管芯的核心区域中的构建块。构建块包括核心区域中的至少一个电容器块。RC钳位电路还包括每个的芯片级导电层连接分布式构建块。

2. 发明授权

US07746606B2 ESD protection for integrated circuits having ultra thin gate oxides 有权
标题翻译：具有超薄栅极氧化物的集成电路的ESD保护
公开(公告)号：US07746606B2
公开(公告)日：2010-06-29
申请号：US10990641
申请日：2004-11-16
申请人： Eugene R. Worley
发明人： Eugene R. Worley
IPC分类号： H02H9/00 , H02H3/20
CPC分类号： H01L27/0251 , H01L27/0292
摘要： According to an exemplary embodiment, an integrated circuit includes a first circuit block having a first power bus. The integrated circuit further includes a second circuit block having a second power bus, where the first power bus is isolated from the second power bus. The integrated circuit further includes a first dedicated ESD bus, where the first dedicated ESD bus provides a discharge path from the first power bus to the second power bus and from the second power bus to the first power bus. The first power bus can be coupled to the first dedicated ESD bus by a first pair to bi-directional diodes, and the second power bus can be coupled to the first dedicated ESD bus by a second pair of bi-directional diodes.
摘要翻译：根据示例性实施例，集成电路包括具有第一电力总线的第一电路块。集成电路还包括具有第二电力总线的第二电路块，其中第一电力总线与第二电力总线隔离。集成电路还包括第一专用ESD总线，其中第一专用ESD总线提供从第一电力总线到第二电力总线以及从第二电力总线到第一电力总线的放电路径。第一电源总线可以通过第一对双向二极管耦合到第一专用ESD总线，并且第二电源总线可以通过第二对双向二极管耦合到第一专用ESD总线。

3. 发明授权

US07675127B1 MOSFET having increased snap-back conduction uniformity 有权
标题翻译： MOSFET具有增加的反弹传导均匀性
公开(公告)号：US07675127B1
公开(公告)日：2010-03-09
申请号：US11107206
申请日：2005-04-15
申请人： Eugene R. Worley
发明人： Eugene R. Worley
IPC分类号： H01L29/78
CPC分类号： H01L27/027 , H01L29/0611
摘要： According to an exemplary embodiment, a semiconductor structure includes an NFET situated over a substrate. The semiconductor structure further includes a P+ substrate tie ring surrounded the NFET. The P+ substrate tie ring includes a salicide layer situated on a P+ diffusion region. The semiconductor structure further includes an N well ring situated between the NFET and the P+ substrate tie ring, where the N well ring increases snap-back conduction uniformity in the NFET. The semiconductor structure further includes an N+ active ring situated between the NFET and the P+ substrate tie ring, where the N+ active ring surrounds the NFET and connects the P+ substrate tie ring to the N well ring. The N+ active ring includes a salicide layer situated on an N+ diffusion region, where the salicide layer of the N+ active ring connects the N well ring to the P+ substrate tie ring.
摘要翻译：根据示例性实施例，半导体结构包括位于衬底上的NFET。半导体结构还包括围绕NFET的P +衬底连接环。 P +衬底连接环包括位于P +扩散区上的自对准硅化物层。半导体结构还包括位于NFET和P +衬底连接环之间的N阱环，其中N阱环增加NFET中的卡扣传导均匀性。半导体结构还包括位于NFET和P +衬底连接环之间的N +有源环，其中N +活性环围绕NFET并将P +衬底连接环连接到N阱环。 N +活性环包括位于N +扩散区上的自对准硅化物层，其中N +活性环的自对准硅层将N阱环连接到P +衬底连接环。

4. 发明授权

US4724342A Push-pull DCFL driver circuit 失效
标题翻译：推挽式DCFL驱动电路
公开(公告)号：US4724342A
公开(公告)日：1988-02-09
申请号：US828724
申请日：1986-02-12
申请人： Robert N. Sato , Eugene R. Worley
发明人： Robert N. Sato , Eugene R. Worley
IPC分类号： H03K19/0944 , H03K19/0952 , H03K19/017
CPC分类号： H03K19/09443 , H03K19/0952
摘要： An improved driver circuit for an integrated gate circuit using Gallium Arsenide direct coupled FET logic. The push-pull driver circuit generally comprises an enhancement mode voltage follower transistor for driving a load during a first logic transition, and an enhancement mode pull-down transistor for driving this load during a second logic transition. Since only one of these transistors are conductive during these logic transitions (i.e., LO to HI, and HI to LO), little or no static current flows through these transistor means during steady state conditions. Thus, particularly for large capacitive loads, the driver circuit will be considerably faster than conventional DCFL technology, while not causing a significant increase in the power consumed by the push-pull driver circuit.
摘要翻译：使用砷化镓直接耦合FET逻辑的集成门电路的改进的驱动电路。推挽驱动器电路通常包括用于在第一逻辑转变期间驱动负载的增强模式电压跟随器晶体管，以及用于在第二逻辑转换期间驱动该负载的增强模式下拉晶体管。由于这些晶体管中只有一个在这些逻辑转换期间（即，LO至HI和HI至LO）都是导通的，所以在稳态条件下很少或没有静电流流过这些晶体管。因此，特别是对于大容性负载，驱动电路将比常规DCFL技术快得多，而不会引起推挽驱动电路消耗的功率的显着增加。

5. 发明授权

US08514532B2 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US08514532B2
公开(公告)日：2013-08-20
申请号：US12487528
申请日：2009-06-18
申请人： Eugene R. Worley , Chiew-Guan Tan , Mark R. Tennyson
发明人： Eugene R. Worley , Chiew-Guan Tan , Mark R. Tennyson
IPC分类号： H02H9/00 , H02H3/20 , H02H9/04 , H02H3/22
CPC分类号： H02H9/046
摘要： Disclosed herein are embodiments of electrostatic discharge (ESD) protection circuits. In certain embodiments an ESD protection circuit may include two series resistor-capacitor (RC) circuits. One series RC circuit may have a short time constant and may selectively activate a current shunt between two power rails in response to an ESD event. Accordingly, the ESD circuit may be able to respond to fast ramping ESD events. The other series RC circuit has a longer time constant, and maintains the current shunt in an active state for a sufficient amount of time to allow the ESD event to be completely discharged.
摘要翻译：这里公开了静电放电（ESD）保护电路的实施例。在某些实施例中，ESD保护电路可以包括两个串联电阻 - 电容（RC）电路。一个串联RC电路可以具有短的时间常数，并且可以响应于ESD事件选择性地激活两个电源轨之间的电流分流。因此，ESD电路可能能够响应快速斜坡ESD事件。另一个串联RC电路具有更长的时间常数，并且将电流分流保持在活动状态足够的时间以允许ESD事件被完全放电。

6. 发明申请

US20120236444A1 CHARGE PUMP ELECTROSTATIC DISCHARGE PROTECTION 有权
标题翻译：充电泵静电放电保护
公开(公告)号：US20120236444A1
公开(公告)日：2012-09-20
申请号：US13047683
申请日：2011-03-14
申请人： Ankit Srivastava , Eugene R. Worley , Guoqing Miao , Xiaohong Quan
发明人： Ankit Srivastava , Eugene R. Worley , Guoqing Miao , Xiaohong Quan
IPC分类号： H02H9/04
CPC分类号： H03F1/52 , H01L27/0285 , H02M1/32 , H02M3/07
摘要： Techniques for electrostatic discharge (ESD) protection for amplifiers and other circuitry employing charge pumps. In an exemplary embodiment, a Vneg switch coupling a second flying capacitor node to a negative output voltage node is closed in response to an ESD event being detected between a supply voltage node and the negative output voltage node. A ground switch coupling a ground node to the second flying capacitor node is closed in response to an ESD event being detected between the ground node and the negative output voltage node. The Vneg switch is further closed in response to the ESD event being detected between the ground node and the negative output voltage node. Further techniques are disclosed for providing on-chip snapback clamps at the output of a power amplifier coupled to the charge pump to protect against ESD events as defined by the standard IEC 61000-4-2.
摘要翻译：用于放大器和使用电荷泵的其他电路的静电放电（ESD）保护技术。在示例性实施例中，响应于在电源电压节点和负输出电压节点之间检测到ESD事件，将第二飞跨电容器节点耦合到负输出电压节点的Vneg开关闭合。响应于在接地节点和负输出电压节点之间检测到ESD事件，将接地节点耦合到第二飞跨电容器节点的接地开关闭合。响应于在接地节点和负输出电压节点之间检测到ESD事件，Vneg开关进一步闭合。公开了用于在耦合到电荷泵的功率放大器的输出处提供片上快速恢复钳位以防止由标准IEC 61000-4-2定义的ESD事件的其它技术。

7. 发明授权

US08213142B2 Amplifier with improved ESD protection circuitry 有权
标题翻译：具有改进的ESD保护电路的放大器
公开(公告)号：US08213142B2
公开(公告)日：2012-07-03
申请号：US12260901
申请日：2008-10-29
申请人： Eugene R. Worley
发明人： Eugene R. Worley
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22 , H02H9/06
CPC分类号： H03F1/523 , H01L27/0255 , H03F3/195 , H03F3/45183 , H03F2200/294 , H03F2200/441 , H03F2200/444 , H03F2200/492 , H03F2203/45314 , H03F2203/45386 , H03F2203/45568
摘要： An amplifier (e.g., an LNA) with improved ESD protection circuitry is described. In one exemplary design, the amplifier includes a transistor, an inductor, and a clamp circuit. The transistor has a gate coupled to a pad and provides signal amplification for the amplifier. The inductor is coupled to a source of the transistor and provides source degeneration for the transistor. The clamp circuit is coupled between the gate and source of the transistor and provides ESD protection for the transistor. The clamp circuit may include at least one diode coupled between the gate and source of the transistor. The clamp circuit conducts current through the inductor to generate a voltage drop across the inductor when a large voltage pulse is applied to the pad. The gate-to-source voltage (Vgs) of the transistor is reduced by the voltage drop across the inductor, which may improve the reliability of the transistor.
摘要翻译：描述了具有改进的ESD保护电路的放大器（例如，LNA）。在一个示例性设计中，放大器包括晶体管，电感器和钳位电路。晶体管具有耦合到焊盘并且为放大器提供信号放大的栅极。电感器耦合到晶体管的源极，并为晶体管提供源极退化。钳位电路耦合在晶体管的栅极和源极之间，并为晶体管提供ESD保护。钳位电路可以包括耦合在晶体管的栅极和源极之间的至少一个二极管。当对焊盘施加大的电压脉冲时，钳位电路通过电感器传导电流，以在电感器两端产生电压降。晶体管的栅极 - 源极电压（Vgs）被电感器两端的电压降降低，这可能会提高晶体管的可靠性。

8. 发明授权

US6121087A Integrated circuit device with embedded flash memory and method for manufacturing same 失效
标题翻译：具有嵌入式闪存的集成电路器件及其制造方法
公开(公告)号：US6121087A
公开(公告)日：2000-09-19
申请号：US665783
申请日：1996-06-18
申请人： Richard A. Mann , Eugene R. Worley
发明人： Richard A. Mann , Eugene R. Worley
IPC分类号： H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/78
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546 , H01L29/42328
摘要： The switching properties of the disclosed device, low off current and high on current, also allows the device to be employed to replace EEPROM, fuses, anti-fuses or other electrically-alterable non volatile switching devices in programmable logic devices. The disclosed device can be fabricated with low cost methods. The manufacturing methods are compatible with current tools and procedures which allows the device to be added to CMOS circuits to replace masked ROM with more flexible flash memory at a modest increase in cost. The cell operational method and manufacturing methods allows the size of the memory element to be scaled smaller to maintain a low cost and high performance as the minimum feature size of microelectronic circuits is reduced in the future. The disclosed cell approach also offers simpler programming methods to simplify memory array design, supports higher cell currents for high speed applications, and uses lower cost manufacturing methods than an "ETOX" cell approach. Furthermore, a new etching technique is disclosed which can used in the manufacture of the disclosed cell which allows a very thin gap to be etched in a polysilicon layer.
摘要翻译：所公开的器件的开关特性，低关断电流和高导通电流也允许该器件用于替代可编程逻辑器件中的EEPROM，保险丝，反熔丝或其他可电气改变的非易失性开关器件。所公开的装置可以以低成本的方法制造。制造方法与当前的工具和程序兼容，允许将器件添加到CMOS电路中，以便以适度的成本增加更换具有更灵活的闪存的屏蔽ROM。小区操作方法和制造方法允许随着微电子电路的最小特征尺寸在将来减小而使存储元件的尺寸缩小以保持低成本和高性能。所公开的单元方法还提供了更简单的编程方法来简化存储器阵列设计，支持用于高速应用的更高的单元电流，并且使用比“ETOX”单元方法更低成本的制造方法。此外，公开了一种新的蚀刻技术，其可以用于制造所公开的电池，其允许在多晶硅层中蚀刻非常薄的间隙。

9. 发明授权

US5654862A Method and apparatus for coupling multiple independent on-chip V.sub.dd busses to an ESD core clamp 失效
标题翻译：用于将多个独立片上Vdd总线耦合到ESD芯夹的方法和装置
公开(公告)号：US5654862A
公开(公告)日：1997-08-05
申请号：US732752
申请日：1996-10-18
申请人： Eugene R. Worley , Chilan T. Nguyen , Raymond A. Kjar , Mark R. Tennyson
发明人： Eugene R. Worley , Chilan T. Nguyen , Raymond A. Kjar , Mark R. Tennyson
IPC分类号： H01L27/04 , H01L21/822 , H01L27/06 , H01L29/861 , H03K17/081 , H03K17/16 , H03K19/003 , H02H9/04
CPC分类号： H03K17/162 , H03K17/08104 , H03K19/00315
摘要： A single clamp circuit for integrated circuits with multiple V.sub.dd power pins by coupling the various V.sub.dd busses to an ESD clamped V.sub.dd bus or pseudo- V.sub.dd bus via diodes. The diodes will provide coupling from any V.sub.dd bus to the clamp circuit during a positive ESD transient. A diode for each V.sub.dd bus and a single clamp circuit can be much more area efficient than a single clamp circuit for each V.sub.dd bus. During normal operation, the diodes will become weakly forward biased due to the leakage current of the clamp circuit. Small signal noise will tend not to be coupled from one bus to the other because of the high impedance of the diodes. For a large positive noise transient on one bus, the other bus diode will reverse bias, thus decoupling the signal from the other busses. A large negative noise transient on one bus will cause its diode to reverse bias thus decoupling it from the other busses. To help filter small signal noise and provide an additional charged device model discharge path, a capacitor is added from the pseudo or ESD V.sub.dd to substrate ground. Also disclosed is an ESD protection scheme for allowing a pad voltage to exceed the power supply voltage without using an avalanching junction as the ESD protection means. Further disclosed is a clamp scheme for allowing the transistors of the power supply clamp to see voltages lower than that of the pad voltage which exceed the process reliability limits.
摘要翻译：用于具有多个Vdd电源引脚的集成电路的单钳位电路，通过二极管将各种Vdd总线连接到ESD钳位的Vdd总线或伪Vdd总线。在正ESD静态瞬变期间，二极管将提供任何Vdd总线到钳位电路的耦合。每个Vdd总线和单个钳位电路的二极管可以比每个Vdd总线的单个钳位电路的面积效率更高。在正常工作期间，由于钳位电路的漏电流，二极管将变弱弱正向偏置。由于二极管的高阻抗，小信号噪声往往不会从一个总线耦合到另一个总线。对于一个总线上的大的正噪声瞬态，另一个总线二极管将反向偏置，从而将信号与其他总线分离。一个总线上的大的负噪声瞬变会导致其二极管反向偏置，从而将其与其他总线分离。为了帮助滤除小信号噪声并提供额外的充电器件型放电路径，从伪或ESD Vdd添加到电容器到衬底接地。还公开了一种用于允许焊盘电压超过电源电压而不使用雪崩接点作为ESD保护装置的ESD保护方案。进一步公开的是用于允许电源钳位的晶体管看到低于超过工艺可靠性限制的焊盘电压的电压的钳位方案。

10. 发明授权

US5124578A Receiver designed with large output drive and having unique input protection circuit 失效
标题翻译：接收机设计具有大输出驱动和独特的输入保护电路
公开(公告)号：US5124578A
公开(公告)日：1992-06-23
申请号：US591164
申请日：1990-10-01
申请人： Eugene R. Worley , Howard K. Lane , Winston W. Walker
发明人： Eugene R. Worley , Howard K. Lane , Winston W. Walker
IPC分类号： G06F1/10 , H01L27/02 , H03K5/15 , H03K17/0812 , H03K19/003 , H03K19/0185
CPC分类号： H03K5/15013 , G06F1/10 , H03K17/08122 , H03K19/00315 , H03K19/018521 , H01L27/0251
摘要： A high voltage level input protection, high capacitance output IC clock receiver uses a ratioed CMOS buffer for the output drive and the receiver includes a low resistance input circuit having a pair of series connected large area input diodes physically located beneath the pad in an input network including a pair of gate controlled diodes in parallel therewith and a low value input resistor connected between the pad diodes and the gate controlled diodes. An N+ resistor receives the CMOS level output on a large metal bus from which metal interconnects fan-out to apply the clock signal to a plurality of loads in synchronism with diminished delay and increased reliability. Thus, reducing the resistance required in the input protection circuit improves the synchronism.Synchronism between the original clock signal input and the single diminished delay of the clock signal output from the CMOS buffer is maintained due to the 1 nanosecond clock input rise and fall time inherent in the subject clock receiver due to the low impedance (10 ohms) of the under the pad large diodes, the protection network input resistor of extremely low value (60 ohms) which accounts for the fast rise and fall time and permits the use of the large single delay buffer with fast rise and fall time.
摘要翻译：高电平电平输入保护，高电容输出IC时钟接收器使用用于输出驱动的比率CMOS缓冲器，并且接收器包括低电阻输入电路，其具有物理地位于输入网络中的焊盘下方的一对串联连接的大面积输入二极管包括与其并联的一对栅极控制二极管和连接在焊盘二极管和栅极控制二极管之间的低值输入电阻器。 N +电阻器接收大型金属总线上的CMOS电平输出，金属互连扇出，将时钟信号施加到多个负载，同步延迟和增加的可靠性。因此，降低输入保护电路中所需的电阻提高了同步性。由于本体时钟接收机固有的1纳秒时钟输入上升和下降时间，由于低阻抗（10欧姆），保持原始时钟信号输入和从CMOS缓冲器输出的时钟信号单个减小的延迟之间的同步在垫下大二极管，保护网络输入电阻值极低（60欧姆），占快速上升和下降时间，允许使用具有快速上升和下降时间的大单个延迟缓冲器。

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