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1. 发明申请

US20120105167A1 PACKAGE INDUCTANCE COMPENSATING TUNABLE CAPACITOR CIRCUIT 有权
标题翻译：封装电感补偿电容电路
公开(公告)号：US20120105167A1
公开(公告)日：2012-05-03
申请号：US12916338
申请日：2010-10-29
申请人： ByungWook Min , Der-Woei Wu
发明人： ByungWook Min , Der-Woei Wu
IPC分类号： H03H7/00
CPC分类号： H03J3/20 , H01L23/66 , H01L2924/0002 , H03J2200/10 , H01L2924/00
摘要： An integrated circuit (IC) for compensating for a package inductance is disclosed. A first ground pad is directly connected to an on-chip ground node. A second IC ground pad is connected to the on-chip ground node via a tunable capacitor circuit, where the capacitance of the tunable capacitor circuit resonates with the package inductance at the operating frequency of the IC.
摘要翻译：公开了一种用于补偿封装电感的集成电路（IC）。第一接地焊盘直接连接到片上接地节点。第二个IC接地焊盘通过可调电容电路连接到片上接地节点，其中可调电容电路的电容在IC工作频率下与封装电感谐振。

2. 发明授权

US08791767B2 Package inductance compensating tunable capacitor circuit 有权
标题翻译：封装电感补偿可调电容电路
公开(公告)号：US08791767B2
公开(公告)日：2014-07-29
申请号：US12916338
申请日：2010-10-29
申请人： ByungWook Min , Der-Woei Wu
发明人： ByungWook Min , Der-Woei Wu
IPC分类号： H03H7/00
CPC分类号： H03J3/20 , H01L23/66 , H01L2924/0002 , H03J2200/10 , H01L2924/00
摘要： An integrated circuit (IC) for compensating for a package inductance is disclosed. A first ground pad is directly connected to an on-chip ground node. A second IC ground pad is connected to the on-chip ground node via a tunable capacitor circuit, where the capacitance of the tunable capacitor circuit resonates with the package inductance at the operating frequency of the IC.
摘要翻译：公开了一种用于补偿封装电感的集成电路（IC）。第一接地焊盘直接连接到片上接地节点。第二个IC接地焊盘通过可调电容电路连接到片上接地节点，其中可调电容电路的电容在IC工作频率下与封装电感谐振。

3. 发明申请

US20110176245A1 HIGH VOLTAGE, HIGH FREQUENCY ESD PROTECTION CIRCUIT FOR RF ICs 有权
标题翻译：用于RF IC的高电压，高频ESD保护电路
公开(公告)号：US20110176245A1
公开(公告)日：2011-07-21
申请号：US12748067
申请日：2010-03-26
申请人： Eugene R. Worley , ByungWook Min , Der-woei Wu
发明人： Eugene R. Worley , ByungWook Min , Der-woei Wu
IPC分类号： H02H9/00
CPC分类号： H03F1/52 , H01L27/0274
摘要： Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse. Alternate embodiments further reduce the capacitance of the ESD protection circuit by using only a positive ESD clamp to provide ESD protection during a positive ESD pulse while protection for a negative ESD pulse is provided by a discharge path formed by a path of an RF front-end switch coupled to a negative ESD diode.
摘要翻译：描述了需要高压和高频操作的RFIC的改进的ESD保护电路。与预充电电路和二极管网络相结合的共源共栅接地栅极复位NFET（GGNFET）导致具有低电容和高导通电压的正ESD保护钳位。正电压ESD保护钳在正电压ESD脉冲期间为IC提供ESD保护。公开了一种负ESD保护钳的示例性实施例，其中使用偏置电路或电荷泵代替预充电电路，以允许偏置电路或电荷泵与二极管网络和共源共栅接地的组合门复位NFET，以提供防止负ESD电压脉冲的保护。在正或负电压ESD脉冲期间，正和负ESD保护钳的组合可为IC提供ESD保护。替代实施例通过仅使用正的ESD钳位来在正的ESD脉冲期间提供ESD保护来进一步减小ESD保护电路的电容，同时通过由RF前端的路径形成的放电路径来提供负的ESD脉冲的保护开关耦合到负ESD二极管。

4. 发明授权

US08427796B2 High voltage, high frequency ESD protection circuit for RF ICs 有权
标题翻译： RF IC的高压，高频ESD保护电路
公开(公告)号：US08427796B2
公开(公告)日：2013-04-23
申请号：US12748067
申请日：2010-03-26
申请人： Eugene R. Worley , ByungWook Min , Der-woei Wu
发明人： Eugene R. Worley , ByungWook Min , Der-woei Wu
IPC分类号： H02H9/00
CPC分类号： H03F1/52 , H01L27/0274
摘要： Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse. Alternate embodiments further reduce the capacitance of the ESD protection circuit by using only a positive ESD clamp to provide ESD protection during a positive ESD pulse while protection for a negative ESD pulse is provided by a discharge path formed by a path of an RF front-end switch coupled to a negative ESD diode.
摘要翻译：描述了需要高压和高频操作的RFIC的改进的ESD保护电路。与预充电电路和二极管网络相结合的共源共栅接地栅极复位NFET（GGNFET）导致具有低电容和高导通电压的正ESD保护钳位。正电压ESD保护钳在正电压ESD脉冲期间为IC提供ESD保护。公开了一种负ESD保护钳的示例性实施例，其中使用偏置电路或电荷泵代替预充电电路，以允许偏置电路或电荷泵与二极管网络和共源共栅接地的组合门复位NFET，以提供防止负ESD电压脉冲的保护。在正或负电压ESD脉冲期间，正和负ESD保护钳的组合可为IC提供ESD保护。替代实施例通过仅使用正的ESD钳位来在正的ESD脉冲期间提供ESD保护来进一步减小ESD保护电路的电容，同时通过由RF前端的路径形成的放电路径来提供负的ESD脉冲的保护开关耦合到负ESD二极管。

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