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1. 发明申请

US20120224284A1 DISTRIBUTED BUILDING BLOCKS OF R-C CLAMPING CIRCUITRY IN SEMICONDUCTOR DIE CORE AREA 有权
标题翻译：半导体芯片领域的R-C钳位电路分布式建筑块
公开(公告)号：US20120224284A1
公开(公告)日：2012-09-06
申请号：US13173977
申请日：2011-06-30
申请人： Reza Jalilizeinali , Evan Siansuri , Sreeker R. Dundigal , Eugene R. Worley
发明人： Reza Jalilizeinali , Evan Siansuri , Sreeker R. Dundigal , Eugene R. Worley
IPC分类号： H02H9/04 , H05K3/30
CPC分类号： H01L27/0285 , H01L27/0296 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes resistor-capacitor (RC) clamping circuitry for electrostatic discharge (ESD) protection of the semiconductor die. The RC clamping circuitry includes building blocks distributed in the pad ring and in the core area of the semiconductor die, The building blocks include at least one capacitor block in the core area, The RC clamping circuitry also includes chip level conductive layer connections between each of the distributed building blocks.
摘要翻译：半导体管芯包括用于半导体管芯的静电放电（ESD）保护的电阻 - 电容（RC）钳位电路。 RC钳位电路包括分布在焊盘环和半导体管芯的核心区域中的构建块。构建块包括核心区域中的至少一个电容器块。RC钳位电路还包括每个的芯片级导电层连接分布式构建块。

2. 发明授权

US08531806B2 Distributed building blocks of R-C clamping circuitry in semiconductor die core area 有权
标题翻译：半导体芯片区域中R-C钳位电路的分布式构建块
公开(公告)号：US08531806B2
公开(公告)日：2013-09-10
申请号：US13173977
申请日：2011-06-30
申请人： Reza Jalilizeinali , Evan Siansuri , Sreeker R. Dundigal , Eugene R. Worley
发明人： Reza Jalilizeinali , Evan Siansuri , Sreeker R. Dundigal , Eugene R. Worley
IPC分类号： H02H3/22
CPC分类号： H01L27/0285 , H01L27/0296 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes resistor-capacitor (RC) clamping circuitry for electrostatic discharge (ESD) protection of the semiconductor die. The RC clamping circuitry includes building blocks distributed in the pad ring and in the core area of the semiconductor die. The building blocks include at least one capacitor block in the core area. The RC clamping circuitry also includes chip level conductive layer connections between each of the distributed building blocks.
摘要翻译：半导体管芯包括用于半导体管芯的静电放电（ESD）保护的电阻 - 电容（RC）钳位电路。 RC钳位电路包括分布在焊盘环和半导体管芯的芯区域中的构建块。构建块包括核心区域中的至少一个电容器块。 RC钳位电路还包括每个分布式构建块之间的芯片级导电层连接。

3. 发明申请

US20110084362A1 Active Diode Having No Gate and No Shallow Trench Isolation 有权
标题翻译：没有门的活性二极管和没有浅沟槽隔离
公开(公告)号：US20110084362A1
公开(公告)日：2011-04-14
申请号：US12751903
申请日：2010-03-31
申请人： Reza Jalilizeinali , Eugene R. Worley , Evan Siansuri , Sreeker R. Dundigal
发明人： Reza Jalilizeinali , Eugene R. Worley , Evan Siansuri , Sreeker R. Dundigal
IPC分类号： H01L29/861 , H01L21/762
CPC分类号： H01L29/8611 , H01L29/0692 , H01L29/66128
摘要： An active diode with fast turn-on time, low capacitance, and low turn-on resistance may be manufactured without a gate and without a shallow trench isolation region between doped regions of the diode. A short conduction path in the active diode allows a fast turn-on time, and a lack of gate oxide reduces susceptibility of the active diode to extreme voltages. The active diode may be implemented in integrated circuits to prevent and reduce damage from electrostatic discharge (ESD) events. Manufacturing the active diode is accomplished by depositing a salicide block between doped regions of the diode before salicidation. After the salicide layers are formed on the doped regions, the salicide block is removed.
摘要翻译：可以在没有栅极并且在二极管的掺杂区域之间没有浅沟槽隔离区域的情况下制造具有快导通时间，低电容和低导通电阻的有源二极管。有源二极管中的短导通路径允许快速导通时间，并且缺少栅极氧化物降低有源二极管对极端电压的敏感性。有源二极管可以在集成电路中实现，以防止和减少静电放电（ESD）事件的损坏。有源二极管的制造是通过在盐析之前在二极管的掺杂区域之间沉积自对准硅化物块来实现的。在掺杂区域上形成自对准硅化物层之后，去除硅化物块。

4. 发明授权

US09368648B2 Active diode having no gate and no shallow trench isolation 有权
标题翻译：有源二极管没有栅极，没有浅沟槽隔离
公开(公告)号：US09368648B2
公开(公告)日：2016-06-14
申请号：US12751903
申请日：2010-03-31
申请人： Reza Jalilizeinali , Eugene R. Worley , Evan Siansuri , Sreeker R. Dundigal
发明人： Reza Jalilizeinali , Eugene R. Worley , Evan Siansuri , Sreeker R. Dundigal
IPC分类号： H01L27/02 , H01L29/861 , H01L29/66 , H01L29/06
CPC分类号： H01L29/8611 , H01L29/0692 , H01L29/66128
摘要： An active diode with fast turn-on time, low capacitance, and low turn-on resistance may be manufactured without a gate and without a shallow trench isolation region between doped regions of the diode. A short conduction path in the active diode allows a fast turn-on time, and a lack of gate oxide reduces susceptibility of the active diode to extreme voltages. The active diode may be implemented in integrated circuits to prevent and reduce damage from electrostatic discharge (ESD) events. Manufacturing the active diode is accomplished by depositing a salicide block between doped regions of the diode before salicidation. After the salicide layers are formed on the doped regions, the salicide block is removed.
摘要翻译：可以在没有栅极并且在二极管的掺杂区域之间没有浅沟槽隔离区域的情况下制造具有快导通时间，低电容和低导通电阻的有源二极管。有源二极管中的短导通路径允许快速导通时间，并且缺少栅极氧化物降低有源二极管对极端电压的敏感性。有源二极管可以在集成电路中实现，以防止和减少静电放电（ESD）事件的损坏。有源二极管的制造是通过在盐析之前在二极管的掺杂区域之间沉积自对准硅化物块来实现的。在掺杂区域上形成自对准硅化物层之后，去除硅化物块。

5. 发明申请

US20120074496A1 Diode Having A Pocket Implant Blocked And Circuits And Methods Employing Same 有权
标题翻译：具有口袋植入物阻塞的二极管和使用相同的电路和方法
公开(公告)号：US20120074496A1
公开(公告)日：2012-03-29
申请号：US13075701
申请日：2011-03-30
申请人： Reza Jalilizeinali , Eugene R. Worley , Evan Siansuri , Sreeker Dundigal
发明人： Reza Jalilizeinali , Eugene R. Worley , Evan Siansuri , Sreeker Dundigal
IPC分类号： H01L23/62 , B05C11/00 , H01L21/762 , H01L29/78 , H01L29/861
CPC分类号： H01L29/66356 , H01L27/0255 , H01L29/0649 , H01L29/6609 , H01L29/7391 , H01L29/861 , H01L2924/0002 , H04B1/109 , H04B1/48 , H01L2924/00
摘要： Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance.
摘要翻译：提供包括门控二极管和浅沟槽隔离（STI）二极管，制造方法和相关电路的二极管，而不需要至少一个卤素或口袋注入，从而减小二极管的电容。以这种方式，二极管可以用于对负载电容具有敏感性的电路和其它器件，同时仍然获得二极管的性能特性。栅极二极管的这种特性包括快速接通时间和高电导，使得门极二极管非常适合于静电放电（ESD）保护电路。二极管包括具有阱区和其上的绝缘层的半导体衬底。在绝缘层上形成栅电极。阳极和阴极区域设置在阱区中。形成P-N结。在二极管中阻塞至少一个口袋植入物以减少电容。

6. 发明授权

US08665570B2 Diode having a pocket implant blocked and circuits and methods employing same 有权
标题翻译：具有口袋植入物的二极管被阻塞，电路和采用其的方法
公开(公告)号：US08665570B2
公开(公告)日：2014-03-04
申请号：US13075701
申请日：2011-03-30
申请人： Reza Jalilizeinali , Eugene R. Worley , Evan Siansuri , Sreeker Dundigal
发明人： Reza Jalilizeinali , Eugene R. Worley , Evan Siansuri , Sreeker Dundigal
IPC分类号： H02H9/00
CPC分类号： H01L29/66356 , H01L27/0255 , H01L29/0649 , H01L29/6609 , H01L29/7391 , H01L29/861 , H01L2924/0002 , H04B1/109 , H04B1/48 , H01L2924/00
摘要： Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance.
摘要翻译：提供包括门控二极管和浅沟槽隔离（STI）二极管，制造方法和相关电路的二极管，而不需要至少一个卤素或口袋注入，从而减小二极管的电容。以这种方式，二极管可以用于对负载电容具有敏感性的电路和其它器件，同时仍然获得二极管的性能特性。栅极二极管的这种特性包括快速接通时间和高电导，使得门极二极管非常适合于静电放电（ESD）保护电路。二极管包括具有阱区和其上的绝缘层的半导体衬底。在绝缘层上形成栅电极。阳极和阴极区域设置在阱区中。形成P-N结。在二极管中阻塞至少一个口袋植入物以减少电容。

7. 发明授权

US07746606B2 ESD protection for integrated circuits having ultra thin gate oxides 有权
标题翻译：具有超薄栅极氧化物的集成电路的ESD保护
公开(公告)号：US07746606B2
公开(公告)日：2010-06-29
申请号：US10990641
申请日：2004-11-16
申请人： Eugene R. Worley
发明人： Eugene R. Worley
IPC分类号： H02H9/00 , H02H3/20
CPC分类号： H01L27/0251 , H01L27/0292
摘要： According to an exemplary embodiment, an integrated circuit includes a first circuit block having a first power bus. The integrated circuit further includes a second circuit block having a second power bus, where the first power bus is isolated from the second power bus. The integrated circuit further includes a first dedicated ESD bus, where the first dedicated ESD bus provides a discharge path from the first power bus to the second power bus and from the second power bus to the first power bus. The first power bus can be coupled to the first dedicated ESD bus by a first pair to bi-directional diodes, and the second power bus can be coupled to the first dedicated ESD bus by a second pair of bi-directional diodes.
摘要翻译：根据示例性实施例，集成电路包括具有第一电力总线的第一电路块。集成电路还包括具有第二电力总线的第二电路块，其中第一电力总线与第二电力总线隔离。集成电路还包括第一专用ESD总线，其中第一专用ESD总线提供从第一电力总线到第二电力总线以及从第二电力总线到第一电力总线的放电路径。第一电源总线可以通过第一对双向二极管耦合到第一专用ESD总线，并且第二电源总线可以通过第二对双向二极管耦合到第一专用ESD总线。

8. 发明授权

US07675127B1 MOSFET having increased snap-back conduction uniformity 有权
标题翻译： MOSFET具有增加的反弹传导均匀性
公开(公告)号：US07675127B1
公开(公告)日：2010-03-09
申请号：US11107206
申请日：2005-04-15
申请人： Eugene R. Worley
发明人： Eugene R. Worley
IPC分类号： H01L29/78
CPC分类号： H01L27/027 , H01L29/0611
摘要： According to an exemplary embodiment, a semiconductor structure includes an NFET situated over a substrate. The semiconductor structure further includes a P+ substrate tie ring surrounded the NFET. The P+ substrate tie ring includes a salicide layer situated on a P+ diffusion region. The semiconductor structure further includes an N well ring situated between the NFET and the P+ substrate tie ring, where the N well ring increases snap-back conduction uniformity in the NFET. The semiconductor structure further includes an N+ active ring situated between the NFET and the P+ substrate tie ring, where the N+ active ring surrounds the NFET and connects the P+ substrate tie ring to the N well ring. The N+ active ring includes a salicide layer situated on an N+ diffusion region, where the salicide layer of the N+ active ring connects the N well ring to the P+ substrate tie ring.
摘要翻译：根据示例性实施例，半导体结构包括位于衬底上的NFET。半导体结构还包括围绕NFET的P +衬底连接环。 P +衬底连接环包括位于P +扩散区上的自对准硅化物层。半导体结构还包括位于NFET和P +衬底连接环之间的N阱环，其中N阱环增加NFET中的卡扣传导均匀性。半导体结构还包括位于NFET和P +衬底连接环之间的N +有源环，其中N +活性环围绕NFET并将P +衬底连接环连接到N阱环。 N +活性环包括位于N +扩散区上的自对准硅化物层，其中N +活性环的自对准硅层将N阱环连接到P +衬底连接环。

9. 发明授权

US4724342A Push-pull DCFL driver circuit 失效
标题翻译：推挽式DCFL驱动电路
公开(公告)号：US4724342A
公开(公告)日：1988-02-09
申请号：US828724
申请日：1986-02-12
申请人： Robert N. Sato , Eugene R. Worley
发明人： Robert N. Sato , Eugene R. Worley
IPC分类号： H03K19/0944 , H03K19/0952 , H03K19/017
CPC分类号： H03K19/09443 , H03K19/0952
摘要： An improved driver circuit for an integrated gate circuit using Gallium Arsenide direct coupled FET logic. The push-pull driver circuit generally comprises an enhancement mode voltage follower transistor for driving a load during a first logic transition, and an enhancement mode pull-down transistor for driving this load during a second logic transition. Since only one of these transistors are conductive during these logic transitions (i.e., LO to HI, and HI to LO), little or no static current flows through these transistor means during steady state conditions. Thus, particularly for large capacitive loads, the driver circuit will be considerably faster than conventional DCFL technology, while not causing a significant increase in the power consumed by the push-pull driver circuit.
摘要翻译：使用砷化镓直接耦合FET逻辑的集成门电路的改进的驱动电路。推挽驱动器电路通常包括用于在第一逻辑转变期间驱动负载的增强模式电压跟随器晶体管，以及用于在第二逻辑转换期间驱动该负载的增强模式下拉晶体管。由于这些晶体管中只有一个在这些逻辑转换期间（即，LO至HI和HI至LO）都是导通的，所以在稳态条件下很少或没有静电流流过这些晶体管。因此，特别是对于大容性负载，驱动电路将比常规DCFL技术快得多，而不会引起推挽驱动电路消耗的功率的显着增加。

10. 发明授权

US08514532B2 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US08514532B2
公开(公告)日：2013-08-20
申请号：US12487528
申请日：2009-06-18
申请人： Eugene R. Worley , Chiew-Guan Tan , Mark R. Tennyson
发明人： Eugene R. Worley , Chiew-Guan Tan , Mark R. Tennyson
IPC分类号： H02H9/00 , H02H3/20 , H02H9/04 , H02H3/22
CPC分类号： H02H9/046
摘要： Disclosed herein are embodiments of electrostatic discharge (ESD) protection circuits. In certain embodiments an ESD protection circuit may include two series resistor-capacitor (RC) circuits. One series RC circuit may have a short time constant and may selectively activate a current shunt between two power rails in response to an ESD event. Accordingly, the ESD circuit may be able to respond to fast ramping ESD events. The other series RC circuit has a longer time constant, and maintains the current shunt in an active state for a sufficient amount of time to allow the ESD event to be completely discharged.
摘要翻译：这里公开了静电放电（ESD）保护电路的实施例。在某些实施例中，ESD保护电路可以包括两个串联电阻 - 电容（RC）电路。一个串联RC电路可以具有短的时间常数，并且可以响应于ESD事件选择性地激活两个电源轨之间的电流分流。因此，ESD电路可能能够响应快速斜坡ESD事件。另一个串联RC电路具有更长的时间常数，并且将电流分流保持在活动状态足够的时间以允许ESD事件被完全放电。

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