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11. 发明授权

US06807119B2 Array containing charge storage and dummy transistors and method of operating the array 有权
公开(公告)号：US06807119B2
公开(公告)日：2004-10-19
申请号：US10325737
申请日：2002-12-23
申请人： Luca Fasoli , Alper Ilkbahar , Roy Scheuerlein
发明人： Luca Fasoli , Alper Ilkbahar , Roy Scheuerlein
IPC分类号： G11C700
CPC分类号： G11C16/0416
摘要： An array of transistors includes a plurality of charge storage transistors and a plurality of dummy transistors interspersed with the plurality of charge storage transistors. Each of the plurality of the dummy transistors is made using the same photolithographic masking steps as each of the plurality of the charge storage transistors. A method of operating the array includes programming and/or erasing the array of transistors, and reading the plurality of charge storage transistors but not the plurality of dummy transistors.

12. 发明授权

US07132335B2 Semiconductor device with localized charge storage dielectric and method of making same 有权
标题翻译：具有局部电荷存储电介质的半导体器件及其制造方法
公开(公告)号：US07132335B2
公开(公告)日：2006-11-07
申请号：US10965763
申请日：2004-10-18
申请人： Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker , Luca Fasoli
发明人： Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker , Luca Fasoli
IPC分类号： H01L21/336
CPC分类号： H01L29/66833 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/792
摘要： An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.
摘要翻译：晶体管阵列包括多个晶体管，沿第一方向延伸的多个字线和沿第二方向延伸的多个位线。每个晶体管包括源极，漏极，沟道和局部电荷存储电介质。所述多个晶体管中的第一晶体管和所述多个晶体管中的第二晶体管共用公共源极/漏极。第一晶体管的第一局部电荷存储电介质不与公共源极/漏极重叠，并且第二晶体管的第二局部电荷存储电介质与公共源极/漏极重叠。

13. 发明授权

US06849905B2 Semiconductor device with localized charge storage dielectric and method of making same 有权
标题翻译：具有局部电荷存储电介质的半导体器件及其制造方法
公开(公告)号：US06849905B2
公开(公告)日：2005-02-01
申请号：US10325951
申请日：2002-12-23
申请人： Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker , Luca Fasoli
发明人： Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker , Luca Fasoli
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L29/792 , H01L29/72
CPC分类号： H01L29/66833 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/792
摘要： An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.
摘要翻译：晶体管阵列包括多个晶体管，沿第一方向延伸的多个字线和沿第二方向延伸的多个位线。每个晶体管包括源极，漏极，沟道和局部电荷存储电介质。所述多个晶体管中的第一晶体管和所述多个晶体管中的第二晶体管共用公共源极/漏极。第一晶体管的第一局部电荷存储电介质不与公共源极/漏极重叠，并且第二晶体管的第二局部电荷存储电介质与公共源极/漏极重叠。

14. 发明申请

US20070263423A1 THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED ARRAY LINE MEMORY ARRAY 有权
标题翻译：配有SEGMENTED阵列线记忆阵列的三维存储器件
公开(公告)号：US20070263423A1
公开(公告)日：2007-11-15
申请号：US11764789
申请日：2007-06-18
申请人： Roy Scheuerlein , Alper Ilkbahar , Luca Fasoli
发明人： Roy Scheuerlein , Alper Ilkbahar , Luca Fasoli
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.
摘要翻译：三维（3D）高密度存储器阵列包括多个分段位线（即感测线），其中存储器阵列内的段切换器件将段连接到全局位线。分段交换设备驻留在集成电路的一个或多个层上，优选地驻留在每个位线层上。全局位线优选地位于存储器阵列下方的一个层上，但可驻留在多于一个层上。位线段优选地共享到相关联的全局位线的垂直连接。在某些EEPROM实施例中，该阵列包括多层分段位线，其中多层具有段连接开关，并且共享与全局位线层的垂直连接。这样的存储器阵列可以通过对于半选择的存储器单元的更少的写入干扰效应来实现，并且可以用要被擦除的小得多的单元块来实现。

15. 发明申请

US20120106253A1 THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED ARRAY LINE MEMORY ARRAY 有权
标题翻译：配有SEGMENTED阵列线记忆阵列的三维存储器件
公开(公告)号：US20120106253A1
公开(公告)日：2012-05-03
申请号：US13348336
申请日：2012-01-11
申请人： Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli
发明人： Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli
IPC分类号： G11C5/06 , G11C16/04
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.
摘要翻译：三维（3D）高密度存储器阵列包括多个分段位线（即感测线），其中存储器阵列内的段切换器件将段连接到全局位线。分段交换设备驻留在集成电路的一个或多个层上，优选地驻留在每个位线层上。全局位线优选地位于存储器阵列下方的一个层上，但可驻留在多于一个层上。位线段优选地共享到相关联的全局位线的垂直连接。在某些EEPROM实施例中，该阵列包括多层分段位线，其中多层具有段连接开关，并且共享与全局位线层的垂直连接。这样的存储器阵列可以通过对于半选择的存储器单元的更少的写入干扰效应来实现，并且可以用要被擦除的小得多的单元块来实现。

16. 发明授权

US07233024B2 Three-dimensional memory device incorporating segmented bit line memory array 有权
标题翻译：结合分段位线存储器阵列的三维存储器件
公开(公告)号：US07233024B2
公开(公告)日：2007-06-19
申请号：US10403752
申请日：2003-03-31
申请人： Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli
发明人： Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli
IPC分类号： H01L27/10
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.
摘要翻译：三维（3D）高密度存储器阵列包括多个分段位线（即感测线），其中存储器阵列内的段切换器件将段连接到全局位线。分段交换设备驻留在集成电路的一个或多个层上，优选地驻留在每个位线层上。全局位线优选地位于存储器阵列下方的一个层上，但可驻留在多于一个层上。位线段优选地共享到相关联的全局位线的垂直连接。在某些EEPROM实施例中，该阵列包括多层分段位线，其中多层具有段连接开关，并且共享与全局位线层的垂直连接。这样的存储器阵列可以通过对于半选择的存储器单元的更少的写入干扰效应来实现，并且可以用要被擦除的小得多的单元块来实现。

17. 发明授权

US06940109B2 High density 3d rail stack arrays and method of making 有权
标题翻译：高密度三维轨道堆叠阵列及其制作方法
公开(公告)号：US06940109B2
公开(公告)日：2005-09-06
申请号：US10779760
申请日：2004-02-18
申请人： Kedar Patel , Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker
发明人： Kedar Patel , Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker
IPC分类号： H01L21/8239 , H01L27/088 , H01L27/092 , H01L27/105 , H01L29/76
CPC分类号： H01L27/088 , H01L27/092 , H01L27/105 , H01L27/1052
摘要： A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.
摘要翻译：半导体器件包括两个晶体管，其中一个晶体管的栅电极和另一个晶体管的源极或漏极位于同一导轨中。单片三维阵列包含多个这样的装置。阵列的不同级别的晶体管优选地具有不同的取向。

18. 发明授权

US06737675B2 High density 3D rail stack arrays 有权
标题翻译：高密度3D轨道堆叠阵列
公开(公告)号：US06737675B2
公开(公告)日：2004-05-18
申请号：US10180046
申请日：2002-06-27
申请人： Kedar Patel , Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker
发明人： Kedar Patel , Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker
IPC分类号： H01L2976
CPC分类号： H01L27/088 , H01L27/092 , H01L27/105 , H01L27/1052
摘要： A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.
摘要翻译：半导体器件包括两个晶体管，其中一个晶体管的栅电极和另一个晶体管的源极或漏极位于同一导轨中。单片三维阵列包含多个这样的装置。阵列的不同级别的晶体管优选地具有不同的取向。

19. 发明申请

US20050044459A1 Redundant memory structure using bad bit pointers 有权
公开(公告)号：US20050044459A1
公开(公告)日：2005-02-24
申请号：US10961501
申请日：2004-10-08
申请人： Roy Scheuerlein , Mark Johnson , Derek Bosch , Alper Ilkbahar , J. Tringali
发明人： Roy Scheuerlein , Mark Johnson , Derek Bosch , Alper Ilkbahar , J. Tringali
IPC分类号： G11C7/10 , G11C7/24 , G11C29/00 , G11C29/44
CPC分类号： G11C29/76 , G11C7/1006 , G11C7/24 , G11C29/44 , G11C29/4401 , G11C29/78
摘要： The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

20. 发明授权

US08659028B2 Three-dimensional memory device incorporating segmented array line memory array 有权
公开(公告)号：US08659028B2
公开(公告)日：2014-02-25
申请号：US11764789
申请日：2007-06-18
申请人： Roy E. Scheuerlein , Alper Ilkbahar , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： H01L27/10
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.

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