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11. 发明申请

US20080126709A1 ADVANCED PROCESSOR WITH SYSTEM ON A CHIP INTERCONNECT TECHNOLOGY 失效
标题翻译：具有芯片互连技术系统的先进处理器
公开(公告)号：US20080126709A1
公开(公告)日：2008-05-29
申请号：US11961884
申请日：2007-12-20
申请人： David T. Hass , Abbas Rashid
发明人： David T. Hass , Abbas Rashid
IPC分类号： G06F12/08
CPC分类号： H04L45/52 , G06F12/0813 , G06F2212/154 , G06F2212/62 , H04L12/42 , H04L49/00 , H04L49/15 , H04L49/30 , H04L49/35
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

12. 发明授权

US07170902B2 Cross-bar switch incorporating a sink port with retry capability 有权
标题翻译：交叉开关结合了具有重试能力的水槽端口
公开(公告)号：US07170902B2
公开(公告)日：2007-01-30
申请号：US10036762
申请日：2001-12-21
申请人： Abbas Rashid , Nazar Zaidi , Mark Bryers , Fred Gruner
发明人： Abbas Rashid , Nazar Zaidi , Mark Bryers , Fred Gruner
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/102 , H04L12/42 , H04L41/0896 , H04L49/101 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/3018
摘要： A cross-bar switch includes a set of input ports to accept data packets and a set of sink ports in communication with the input ports to forward the data packets. Each sink port includes a communications link interface with a Retry input. When a signal is asserted on the Retry input, the sink port aborts transmission of a data packet and waits a predetermined period of time to retransmit the data packet.
摘要翻译：交叉开关包括一组接收数据分组的输入端口和与输入端口通信的汇聚端口集合以转发数据分组。每个宿端口包括具有重试输入的通信链路接口。当信号在重试输入上有效时，宿端口中止数据包的发送，并等待预定的时间间隔重传数据包。

13. 发明授权

US07068603B2 Cross-bar switch 有权
公开(公告)号：US07068603B2
公开(公告)日：2006-06-27
申请号：US09900514
申请日：2001-07-06
申请人： Abbas Rashid , Nazar Zaidi , Mark Bryers , Fred Gruner
发明人： Abbas Rashid , Nazar Zaidi , Mark Bryers , Fred Gruner
IPC分类号： H04L12/26
CPC分类号： H04L49/102 , H04L12/42 , H04L41/0896 , H04L49/101 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/3018
摘要： A cross-bar switch includes a set of input ports for receiving data packets and a set of sink ports for transmitting the received packets to identified targets. A set of data rings couples the input ports to the sink ports. Each sink port utilizes the set of data rings to simultaneously accept multiple data packets targeted to the same destination—creating a non-blocking cross-bar switch. Sink ports are also each capable of supporting multiple targets—providing the cross-bar switch with implicit multicast capability.

14. 发明申请

US20070165035A1 DEFERRED SHADING GRAPHICS PIPELINE PROCESSOR HAVING ADVANCED FEATURES 有权
标题翻译：具有先进功能的缩减图形管道处理器
公开(公告)号：US20070165035A1
公开(公告)日：2007-07-19
申请号：US11613093
申请日：2006-12-19
申请人： Jerome Duluk , Richard Hessel , Vaughn Arnold , Jack Benkual , Joseph Bratt , George Cuan , Stephen Dodgen , Emerson Fang , Zhaoyu Gong , Thomas Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew Papakipos , Jason Redgrave , Sushma Trivedi , Nathan Tuck , Shun Go , Lindy Fung , Tuan Nguyen , Joseph Grass , Bo Hung , Abraham Mammen , Abbas Rashid , Albert Tsay
发明人： Jerome Duluk , Richard Hessel , Vaughn Arnold , Jack Benkual , Joseph Bratt , George Cuan , Stephen Dodgen , Emerson Fang , Zhaoyu Gong , Thomas Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew Papakipos , Jason Redgrave , Sushma Trivedi , Nathan Tuck , Shun Go , Lindy Fung , Tuan Nguyen , Joseph Grass , Bo Hung , Abraham Mammen , Abbas Rashid , Albert Tsay
IPC分类号： G06T1/20
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

15. 发明授权

US07167181B2 Deferred shading graphics pipeline processor having advanced features 有权
标题翻译：具有高级功能的延迟着色图形流水线处理器
公开(公告)号：US07167181B2
公开(公告)日：2007-01-23
申请号：US10458493
申请日：2003-06-09
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
IPC分类号： G06T1/20 , G06T15/40 , G09G5/00
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺的帧缓冲器和多个阶段隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

16. 发明申请

US20050055504A1 Advanced processor with system on a chip interconnect technology 失效
标题翻译：先进的处理器，采用系统芯片互连技术
公开(公告)号：US20050055504A1
公开(公告)日：2005-03-10
申请号：US10898008
申请日：2004-07-23
申请人： David Hass , Abbas Rashid
发明人： David Hass , Abbas Rashid
IPC分类号： G06F12/08 , H04L12/56 , G06F12/00
CPC分类号： H04L45/52 , G06F12/0813 , G06F2212/154 , G06F2212/62 , H04L12/42 , H04L49/00 , H04L49/15 , H04L49/30 , H04L49/35
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

17. 发明申请

US20050041651A1 Advanced processor with mechanism for fast packet queuing operations 有权
标题翻译：具有快速数据包排队操作机制的高级处理器
公开(公告)号：US20050041651A1
公开(公告)日：2005-02-24
申请号：US10930455
申请日：2004-08-31
申请人： David Hass , Abbas Rashid
发明人： David Hass , Abbas Rashid
IPC分类号： G06F12/08 , H04L12/56 , H04L12/50
CPC分类号： H04L49/00 , G06F12/0813 , H04L49/90
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

18. 发明授权

US07305492B2 Content service aggregation system 有权
标题翻译：内容服务聚合系统
公开(公告)号：US07305492B2
公开(公告)日：2007-12-04
申请号：US10191742
申请日：2002-07-08
申请人： Mark Bryers , Elango Ganesan , Frederick Gruner , David Hass , Robert Hathaway , Ramesh Panwar , Ricardo Ramirez , Abbas Rashid , Mark Vilas , Nazar Zaidi , Yen Lee , Chau Anh Ngoc Nguyen , John Phillips , Yuhong Andy Zhou , Gregory G. Spurrier , Sankar Ramanoorthi , Michael Freed
发明人： Mark Bryers , Elango Ganesan , Frederick Gruner , David Hass , Robert Hathaway , Ramesh Panwar , Ricardo Ramirez , Abbas Rashid , Mark Vilas , Nazar Zaidi , Yen Lee , Chau Anh Ngoc Nguyen , John Phillips , Yuhong Andy Zhou , Gregory G. Spurrier , Sankar Ramanoorthi , Michael Freed
IPC分类号： G06F15/16
CPC分类号： H04L47/125 , H04L29/06 , H04L63/0485
摘要： A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.
摘要翻译：网络内容服务设备包括适于执行一组网络服务的一组计算元件; 以及耦合所述一组计算元件中的计算元件的交换结构。该组网络服务包括防火墙保护，网络地址转换，互联网协议转发，带宽管理，安全套接字层操作，Web缓存，Web交换和虚拟专用网络。在计算元件上可操作的代码实现了网络服务，并且在还包括至少一个输入/输出端口的刀片上提供计算元件。

19. 发明授权

US07082139B2 Cross-bar switch with sink port accepting multiple packets 失效
标题翻译：交叉条交换机，接收端口接收多个报文
公开(公告)号：US07082139B2
公开(公告)日：2006-07-25
申请号：US10037144
申请日：2001-12-21
申请人： Abbas Rashid , Nazar Zaidi , Mark Bryers
发明人： Abbas Rashid , Nazar Zaidi , Mark Bryers
IPC分类号： H04L12/28
CPC分类号： H04L49/102 , H04L12/42 , H04L41/0896 , H04L49/101 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/3018
摘要： A cross-bar switch includes a set of input ports to receive data packets and a set of sink ports in communication with the input ports to receive the data packets and forward them onto a communications link. Each sink port is adapted to concurrently receive multiple data packets targeted to the same destination or multiple destinations. For example, one sink port receives a first data packet and a second data packet. The one sink port receives at least a portion of the second data packet during a time period in which the one sink port is receiving the first data packet.
摘要翻译：交叉开关包括一组用于接收数据分组的输入端口和与输入端口通信的一组汇接器端口，以接收数据分组并将其转发到通信链路上。每个宿端口适于同时接收针对相同目的地或多个目的地的多个数据分组。例如，一个宿端口接收第一数据分组和第二数据分组。一个宿端口在一个宿端口正在接收第一数据分组的时间段期间接收第二数据分组的至少一部分。

20. 发明授权

US07065090B2 Cross-bar switch supporting implicit multicast addressing 有权
标题翻译：交叉开关支持隐式组播寻址
公开(公告)号：US07065090B2
公开(公告)日：2006-06-20
申请号：US10036603
申请日：2001-12-21
申请人： Abbas Rashid , Nazar Zaidi , Mark Bryers
发明人： Abbas Rashid , Nazar Zaidi , Mark Bryers
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L49/102 , H04L12/42 , H04L41/0896 , H04L49/101 , H04L49/201 , H04L49/205 , H04L49/25 , H04L49/3018
摘要： A cross-bar switch includes a set of input ports and a set of sink ports in communication with the input ports. The input ports receive packets, which are snooped by the sink ports. The cross-bar switch also includes a set of port address tables. Each port address table is adapted to store data identifying a plurality of destinations supported by a sink port. For example, a first port address table is adapted to identify a plurality of destinations supported by a first sink port in the set of sink ports. When determining whether to accept a packet, a sink port considers whether the packet's destination is identified in the sink port's port address table. By supporting multiple destinations, a port address table implicitly facilitates a sink port's multicast operation.
摘要翻译：交叉开关包括一组输入端口和一组与输入端口通信的端口端口。输入端口接收由接收端口窥探的数据包。交叉开关还包括一组端口地址表。每个端口地址表适于存储识别由宿端口支持的多个目的地的数据。例如，第一端口地址表适于识别由该汇聚端口集合中的第一宿端口支持的多个目的地。在确定是否接受数据包时，宿端口会考虑数据包的目的地是否在接收端口的端口地址表中被识别。通过支持多个目的地，端口地址表隐式地有助于汇聚端口的多播操作。

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