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1. 发明申请

US20110225398A1 ADVANCED PROCESSOR SCHEDULING IN A MULTITHREADED SYSTEM 审中-公开
标题翻译：高级处理器调度在多个系统中
公开(公告)号：US20110225398A1
公开(公告)日：2011-09-15
申请号：US13115012
申请日：2011-05-24
申请人： David T. Hass , Abbas Rashid
发明人： David T. Hass , Abbas Rashid
IPC分类号： G06F9/312
CPC分类号： H04L49/00 , G06F12/0813 , H04L49/90
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

2. 发明授权

US07334086B2 Advanced processor with system on a chip interconnect technology 失效
标题翻译：先进的处理器，采用系统芯片互连技术
公开(公告)号：US07334086B2
公开(公告)日：2008-02-19
申请号：US10898008
申请日：2004-07-23
申请人： David T. Hass , Abbas Rashid
发明人： David T. Hass , Abbas Rashid
IPC分类号： G06F12/00 , G06F15/173
CPC分类号： H04L45/52 , G06F12/0813 , G06F2212/154 , G06F2212/62 , H04L12/42 , H04L49/00 , H04L49/15 , H04L49/30 , H04L49/35
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

3. 发明授权

US09154443B2 Advanced processor with fast messaging network technology 有权
标题翻译：高级处理器，具有快速消息传递网络技术
公开(公告)号：US09154443B2
公开(公告)日：2015-10-06
申请号：US12582622
申请日：2009-10-20
申请人： David T Hass , Abbas Rashid
发明人： David T Hass , Abbas Rashid
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , H04L12/931 , G06F12/08
CPC分类号： H04L45/52 , G06F12/0813 , G06F2212/154 , G06F2212/62 , H04L12/42 , H04L49/00 , H04L49/15 , H04L49/30 , H04L49/35
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

4. 发明授权

US09088474B2 Advanced processor with interfacing messaging network to a CPU 有权
标题翻译：高级处理器，将消息传递网络连接到CPU
公开(公告)号：US09088474B2
公开(公告)日：2015-07-21
申请号：US10930937
申请日：2004-08-31
申请人： Abbas Rashid , David T. Hass
发明人： Abbas Rashid , David T. Hass
IPC分类号： H04L12/28 , H04L12/931 , G06F12/08
CPC分类号： H04L49/00 , G06F12/0813 , H04L49/109
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

5. 发明授权

US07984268B2 Advanced processor scheduling in a multithreaded system 失效
标题翻译：多线程系统中的高级处理器调度
公开(公告)号：US07984268B2
公开(公告)日：2011-07-19
申请号：US10898007
申请日：2004-07-23
申请人： David T. Hass , Abbas Rashid
发明人： David T. Hass , Abbas Rashid
IPC分类号： G06F9/30
CPC分类号： H04L49/00 , G06F12/0813 , H04L49/90
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

6. 发明授权

US07467243B2 Advanced processor with scheme for optimal packet flow in a multi-processor system on a chip 失效
标题翻译：高级处理器，具有芯片上多处理器系统中最优分组流的方案
公开(公告)号：US07467243B2
公开(公告)日：2008-12-16
申请号：US10930186
申请日：2004-08-31
申请人： Abbas Rashid , David T. Hass
发明人： Abbas Rashid , David T. Hass
IPC分类号： G05B19/408 , G06F15/16
CPC分类号： H04L49/00 , G06F12/0813 , H04L49/109
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

7. 发明授权

US07627717B2 Advanced processor messaging apparatus including fast messaging ring components configured to accomodate point-to-point transfer of non-memory related messages 失效
标题翻译：高级处理器消息传递装置包括被配置为容纳非存储器相关消息的点对点传送的快速消息传送环组件
公开(公告)号：US07627717B2
公开(公告)日：2009-12-01
申请号：US11961884
申请日：2007-12-20
申请人： David T. Hass , Abbas Rashid
发明人： David T. Hass , Abbas Rashid
IPC分类号： G06F12/00 , G06F15/16
CPC分类号： H04L45/52 , G06F12/0813 , G06F2212/154 , G06F2212/62 , H04L12/42 , H04L49/00 , H04L49/15 , H04L49/30 , H04L49/35
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

8. 发明授权

US09069564B1 Weighted instruction count scheduling 有权
标题翻译：加权指令计数调度
公开(公告)号：US09069564B1
公开(公告)日：2015-06-30
申请号：US13396007
申请日：2012-02-14
申请人： Abbas Rashid , David T. Hass
发明人： Abbas Rashid , David T. Hass
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3802
摘要： A method and system are provided for performing efficient and effective scheduling in a multi-threaded system. Dynamic control of scheduling is provided, in which priority weights can be assigned for some or all of the threads in the multi-threaded system. The priority weights are employed to control prioritization of threads and thread instructions by a scheduler. An instruction count for each thread is used in combination with the priority weights to determine the prioritization order in which instructions are fetched and assigned to execution units for processing.
摘要翻译：提供了一种用于在多线程系统中执行有效和有效的调度的方法和系统。提供了调度的动态控制，其中可以为多线程系统中的一些或所有线程分配优先级权重。采用优先级权重来控制调度器对线程和线程指令的优先级。每个线程的指令计数与优先权重组合使用，以确定指令被取出并分配给执行单元进行处理的优先次序顺序。

9. 发明授权

US07924828B2 Advanced processor with mechanism for fast packet queuing operations 有权
标题翻译：具有快速数据包排队操作机制的高级处理器
公开(公告)号：US07924828B2
公开(公告)日：2011-04-12
申请号：US10930455
申请日：2004-08-31
申请人： David T. Hass , Abbas Rashid
发明人： David T. Hass , Abbas Rashid
IPC分类号： H04L12/56
CPC分类号： H04L49/00 , G06F12/0813 , H04L49/90
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

10. 发明申请

US20100042785A1 ADVANCED PROCESSOR WITH FAST MESSAGING NETWORK TECHNOLOGY 有权
标题翻译：具有快速消息传递技术的高级处理器
公开(公告)号：US20100042785A1
公开(公告)日：2010-02-18
申请号：US12582622
申请日：2009-10-20
申请人： David T. Hass , Abbas Rashid
发明人： David T. Hass , Abbas Rashid
IPC分类号： G06F15/76 , G06F12/08 , G06F9/02
CPC分类号： H04L45/52 , G06F12/0813 , G06F2212/154 , G06F2212/62 , H04L12/42 , H04L49/00 , H04L49/15 , H04L49/30 , H04L49/35
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译：高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。消息传递网络耦合到每个处理器核和多个通信端口。在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

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