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    • 17. 发明授权
    • MOS-gated device having a buried gate and process for forming same
    • 具有掩埋栅极的MOS门控器件及其形成工艺
    • US07388254B2
    • 2008-06-17
    • US11091733
    • 2005-03-28
    • Christopher B. KoconJun Zeng
    • Christopher B. KoconJun Zeng
    • H01L29/739
    • H01L29/7813H01L29/0696H01L29/4236H01L29/66348H01L29/66734H01L29/7397
    • An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions. A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer. A process for forming an improved MOS-gate device provides a device whose gate trench is filled to a selected level with a conductive gate material, over which is formed an isolation dielectric layer whose upper surface is substantially coplanar with the upper surface of the upper layer of the device.
    • 改进的沟槽MOS门控器件包括单晶半导体衬底,其上配置有掺杂的上层。 上层在上表面包括具有第一极性的多个重掺杂体区域,并且覆盖在漏极区域上。 上层还在其上表面包括具有与身体区域相反的第二极性的多个重掺杂源区。 栅极沟槽从上层的上表面延伸到漏极区,并且将一个源极区域与另一个源区域分离。 沟槽具有包括介电材料层的底板和侧壁,并且包含填充到选定电平的导电栅极材料和覆盖栅极材料并基本上填充沟槽的介电材料隔离层。 因此,沟槽中的上层电介质材料的上表面与上层的上表面基本上共面。 用于形成改进的MOS栅极器件的工艺提供了一种器件,其栅极沟槽被填充到具有导电栅极材料的选定的电平,在其上形成隔离电介质层,其上表面与上层的上表面基本共面 的设备。