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1. 发明授权

US08547162B2 Integration of MOSFETs in a source-down configuration 有权
标题翻译：将MOSFET集成在降压配置中
公开(公告)号：US08547162B2
公开(公告)日：2013-10-01
申请号：US12964527
申请日：2010-12-09
申请人： Jacek Korec , Christopher B. Kocon , Shuming Xu
发明人： Jacek Korec , Christopher B. Kocon , Shuming Xu
IPC分类号： H03K17/687
CPC分类号： H01L27/088 , H01L27/0629 , H03K17/04123 , H03K17/687
摘要： An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch.
摘要翻译：用于开关模式电源的输出级具有高侧开关，其具有单片集成到第一管芯上的第一功率FET和第一加速FET。低侧开关具有单片集成到第二管芯上的第二功率FET和第二加速FET。半导体器件具有功率FET和加速FET，其以“下降”配置为单位集成。操作开关式电源的输出级的方法交替地接通和断开高侧和低侧开关，并且通过与开关单片集成的加速FET来驱动至少一个开关。

2. 发明申请

US20110148506A1 INTEGRATION OF MOSFETS IN A SOURCE-DOWN CONFIGURATION 有权
标题翻译： MOSFET在SOURCE-DOWN配置中的集成
公开(公告)号：US20110148506A1
公开(公告)日：2011-06-23
申请号：US12964527
申请日：2010-12-09
申请人： Jacek Korec , Christopher B. Kocon , Shuming Xu
发明人： Jacek Korec , Christopher B. Kocon , Shuming Xu
IPC分类号： H03K17/687 , H01L29/66
CPC分类号： H01L27/088 , H01L27/0629 , H03K17/04123 , H03K17/687
摘要： An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch.
摘要翻译：用于开关模式电源的输出级具有高侧开关，其具有单片集成到第一管芯上的第一功率FET和第一加速FET。低侧开关具有单片集成到第二管芯上的第二功率FET和第二加速FET。半导体器件具有功率FET和加速FET，其以“下降”配置为单位集成。操作开关式电源的输出级的方法交替地接通和断开高侧和低侧开关，并且通过与开关单片集成的加速FET来驱动至少一个开关。

3. 发明授权

US07420247B2 Power LDMOS transistor 有权
标题翻译：电源LDMOS晶体管
公开(公告)号：US07420247B2
公开(公告)日：2008-09-02
申请号：US11202981
申请日：2005-08-12
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L29/72
CPC分类号： H01L29/7835 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/4933
摘要： A LDMOS transistor comprises a trench formed through the epitaxial layer at least to the top surface of the substrate, the trench having a bottom surface and a sidewall contacting the source region and the portion of the channel region extending under the source region. A first insulating layer is formed over the upper surface and sidewall surfaces of the conductive gate. A continuous layer of conductive material forming a source contact and a gate shield electrode is formed along the bottom surface and the sidewall of the trench and over the first insulating layer to cover the top and sidewall surfaces of the conductive gate. A second insulating layer is formed over an active area of the transistor, including over the continuous layer of conductive material and filling the trench. A drain electrode can extend over the second insulating layer to substantially cover the active area.
摘要翻译： LDMOS晶体管包括至少通过外延层形成的沟槽，至少到衬底的顶表面，沟槽具有接触源极区域和在源极区域下延伸的沟道区域的部分的底表面和侧壁。在导电栅极的上表面和侧壁表面上形成第一绝缘层。形成源极接触和栅极屏蔽电极的连续导电材料层沿着沟槽的底表面和侧壁形成，并且在第一绝缘层上方覆盖导电栅极的顶表面和侧壁表面。在晶体管的有源区域上形成第二绝缘层，包括在连续的导电材料层上并填充沟槽。漏电极可以在第二绝缘层上延伸以基本覆盖有源区。

4. 发明授权

US07235845B2 Power LDMOS transistor 有权
标题翻译：电源LDMOS晶体管
公开(公告)号：US07235845B2
公开(公告)日：2007-06-26
申请号：US11202968
申请日：2005-08-12
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L29/1083 , H01L29/1087 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/4933
摘要： A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device includes a doped substrate having an epitaxial layer thereover having source and drain implant regions and body and lightly doped drain regions formed therein. The channel region and lightly doped drain regions are doped to a depth to abut the top surface of the substrate. In alternative embodiments, a buffer region of the second conductivity type and having dopant concentration greater than or equal to about the channel region is formed over the top surface of the substrate between the top surface of the substrate and the channel region and lightly doped drain region, wherein the channel region and lightly doped drain regions are doped to a depth to abut the buffer region.
摘要翻译：横向扩散的金属氧化物半导体（LDMOS）晶体管器件包括具有外延层的掺杂衬底，其具有源极和漏极注入区域以及在其中形成的体和轻掺杂漏极区域。沟道区域和轻掺杂漏极区域被掺杂到与衬底的顶表面邻接的深度。在替代实施例中，在衬底的顶表面和沟道区和轻掺杂漏极区之间的衬底的顶表面上形成第二导电类型的缓冲区，并且具有大于或等于沟道区的掺杂浓度，其中沟道区域和轻掺杂漏极区域被掺杂到深度以邻接缓冲区域。

5. 发明申请

US20070138548A1 POWER LDMOS TRANSISTOR 有权
标题翻译：功率LDMOS晶体管
公开(公告)号：US20070138548A1
公开(公告)日：2007-06-21
申请号：US11676613
申请日：2007-02-20
申请人： Christopher Kocon , Shuming Xu , Jacek Korec
发明人： Christopher Kocon , Shuming Xu , Jacek Korec
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7802 , H01L29/7816 , H01L29/7823
摘要： A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.
摘要翻译：横向扩散的金属氧化物半导体晶体管器件包括具有在衬底上形成的半导体层的第一导电类型的衬底。在半导体层中形成第一导电类型的源极区域和漏极延伸区域。在半导体层中形成第二导电类型的体区。导电栅极形成在沟道区域上形成的栅极电介质层上。漏极接触将漏极延伸区域电连接到衬底并且与沟道区域横向间隔开。漏极接触包括形成在半导体层中的衬底和漏极延伸区域之间的高掺杂漏极接触区域，其中高掺杂漏极接触区域的最高部分与半导体层的上表面间隔开。源极触点将源极区域电连接到主体区域。

6. 发明授权

US08614480B2 Power MOSFET with integrated gate resistor and diode-connected MOSFET 有权
标题翻译：功率MOSFET集成栅极电阻和二极管连接的MOSFET
公开(公告)号：US08614480B2
公开(公告)日：2013-12-24
申请号：US13540862
申请日：2012-07-03
申请人： Jun Wang , Shuming Xu , Jacek Korec
发明人： Jun Wang , Shuming Xu , Jacek Korec
IPC分类号： H01L29/66
CPC分类号： H01L27/0629 , H01L27/0727 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/66659 , H01L29/7835 , H01L29/861
摘要： A power MOSFET is formed in a semiconductor device with a parallel combination of a shunt resistor and a diode-connected MOSFET between a gate input node of the semiconductor device and a gate of the power MOSFET. A gate of the diode-connected MOSFET is connected to the gate of the power MOSFET. Source and drain nodes of the diode-connected MOSFET are connected to a source node of the power MOSFET through diodes. The drain node of the diode-connected MOSFET is connected to the gate input node of the semiconductor device. The source node of the diode-connected MOSFET is connected to the gate of the power MOSFET. The power MOSFET and the diode-connected MOSFET are integrated into the substrate of the semiconductor device so that the diode-connected MOSFET source and drain nodes are electrically isolated from the power MOSFET source node through a pn junction.
摘要翻译：在半导体器件的栅极输入节点和功率MOSFET的栅极之间，在半导体器件中形成并联组合的分流电阻器和二极管连接的MOSFET的功率MOSFET。二极管连接的MOSFET的栅极连接到功率MOSFET的栅极。二极管连接的MOSFET的源极和漏极节点通过二极管连接到功率MOSFET的源极节点。二极管连接的MOSFET的漏极节点连接到半导体器件的栅极输入节点。二极管连接的MOSFET的源节点连接到功率MOSFET的栅极。功率MOSFET和二极管连接的MOSFET集成到半导体器件的衬底中，使得二极管连接的MOSFET源极和漏极节点通过pn结与功率MOSFET源节点电隔离。

7. 发明授权

US07589378B2 Power LDMOS transistor 有权
标题翻译：电源LDMOS晶体管
公开(公告)号：US07589378B2
公开(公告)日：2009-09-15
申请号：US11676613
申请日：2007-02-20
申请人： Christopher Boguslaw Kocon , Shuming Xu , Jacek Korec
发明人： Christopher Boguslaw Kocon , Shuming Xu , Jacek Korec
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7802 , H01L29/7816 , H01L29/7823
摘要： A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.
摘要翻译：横向扩散的金属氧化物半导体晶体管器件包括具有在衬底上形成的半导体层的第一导电类型的衬底。在半导体层中形成第一导电类型的源极区域和漏极延伸区域。在半导体层中形成第二导电类型的体区。导电栅极形成在沟道区域上形成的栅极电介质层上。漏极接触将漏极延伸区域电连接到衬底并且与沟道区域横向间隔开。漏极接触包括形成在半导体层中的衬底和漏极延伸区域之间的高掺杂漏极接触区域，其中高掺杂漏极接触区域的最高部分与半导体层的上表面间隔开。源极触点将源极区域电连接到主体区域。

8. 发明授权

US07282765B2 Power LDMOS transistor 有权
标题翻译：电源LDMOS晶体管
公开(公告)号：US07282765B2
公开(公告)日：2007-10-16
申请号：US11180155
申请日：2005-07-13
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7802 , H01L29/7811 , H01L29/7823
摘要： An LDMOS device comprises a substrate having a first conductivity type and a lightly doped epitaxial layer thereon having an upper surface. Source and drain regions of the first conductivity type are formed in the epitaxial layer along with a channel region of a second conductivity type formed therebetween. A conductive gate is formed over a gate dielectric layer. A drain contact electrically connects the drain region to the substrate, comprising a first trench formed from the upper surface of the epitaxial layer to the substrate and having a side wall along the epitaxial layer, a highly doped region of the first conductivity type formed along the side wall of the first trench, and a drain plug in the first trench adjacent the highly doped region. A source contact is provided and an insulating layer is formed between the conductive gate and the source contact.
摘要翻译： LDMOS器件包括具有第一导电类型的衬底和其上具有上表面的轻掺杂外延层。第一导电类型的源区和漏区与其间形成的第二导电类型的沟道区一起形成在外延层中。导电栅极形成在栅极电介质层上。漏极接触将漏极区域电连接到衬底，包括从外延层的上表面到衬底形成的第一沟槽，并且沿着外延层具有侧壁，沿着所述外延层形成的第一导电类型的高掺杂区域沿着所述第一沟槽的侧壁以及与所述高掺杂区域相邻的所述第一沟槽中的排水塞。提供源极触点，并且在导电栅极和源极触点之间形成绝缘层。

9. 发明申请

US20070034942A1 Power LDMOS transistor 有权
标题翻译：电源LDMOS晶体管
公开(公告)号：US20070034942A1
公开(公告)日：2007-02-15
申请号：US11202981
申请日：2005-08-12
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L31/00
CPC分类号： H01L29/7835 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/4933
摘要： A LDMOS transistor comprises a trench formed through the epitaxial layer at least to the top surface of the substrate, the trench having a bottom surface and a sidewall contacting the source region and the portion of the channel region extending under the source region. A first insulating layer is formed over the upper surface and sidewall surfaces of the conductive gate. A continuous layer of conductive material forming a source contact and a gate shield electrode is formed along the bottom surface and the sidewall of the trench and over the first insulating layer to cover the top and sidewall surfaces of the conductive gate. A second insulating layer is formed over an active area of the transistor, including over the continuous layer of conductive material and filling the trench. A drain electrode can extend over the second insulating layer to substantially cover the active area.
摘要翻译： LDMOS晶体管包括至少通过外延层形成的沟槽，至少到衬底的顶表面，沟槽具有接触源极区域和在源极区域下延伸的沟道区域的部分的底表面和侧壁。在导电栅极的上表面和侧壁表面上形成第一绝缘层。形成源极接触和栅极屏蔽电极的连续导电材料层沿着沟槽的底表面和侧壁形成，并且在第一绝缘层上方覆盖导电栅极的顶表面和侧壁表面。在晶体管的有源区域上形成第二绝缘层，包括在连续的导电材料层上并填充沟槽。漏电极可以在第二绝缘层上延伸以基本覆盖有源区。

10. 发明申请

US20070013008A1 Power LDMOS transistor 有权
公开(公告)号：US20070013008A1
公开(公告)日：2007-01-18
申请号：US11180155
申请日：2005-07-13
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L21/337
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7802 , H01L29/7811 , H01L29/7823
摘要： An LDMOS device comprises a substrate having a first conductivity type and a lightly doped epitaxial layer thereon having an upper surface. Source and drain regions of the first conductivity type are formed in the epitaxial layer along with a channel region of a second conductivity type formed therebetween. A conductive gate is formed over a gate dielectric layer. A drain contact electrically connects the drain region to the substrate, comprising a first trench formed from the upper surface of the epitaxial layer to the substrate and having a side wall along the epitaxial layer, a highly doped region of the first conductivity type formed along the side wall of the first trench, and a drain plug in the first trench adjacent the highly doped region. A source contact is provided and an insulating layer is formed between the conductive gate and the source contact.

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