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11. 发明授权

US08812289B1 Simulation that transfers port values of a design block via a configuration block of a programmable device 有权
标题翻译：模拟通过可编程设备的配置块传输设计块的端口值
公开(公告)号：US08812289B1
公开(公告)日：2014-08-19
申请号：US11732642
申请日：2007-04-04
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
IPC分类号： G06F9/455 , G06F17/50 , G06F11/36 , G06F17/22 , G06F11/267
CPC分类号： G06F17/5027 , G06F9/455 , G06F11/267 , G06F11/3652 , G06F17/22 , G06F17/5009 , G06F2217/86
摘要： Approaches for simulating an electronic system. In one approach, a software co-simulation platform is configured to produce a first time sequence of values of a plurality of input ports of a design block of the electronic system, consume a second time sequence of values of a plurality of output ports of the design block, and generate access transactions for transferring the first and second sequences of values. The software co-simulation platform generates a plurality of reconfiguration transactions for transferring reconfiguration data for the design block. A PLD is configured to implement a communication block and a control block. The communication block receives the reconfiguration and access transactions from the software co-simulation platform, and the control block reconfigures programmable logic and interconnect resources of the PLD in response to the reconfiguration transactions. The control block also controls the emulation of the design block in response to the access transactions.
摘要翻译：模拟电子系统的方法。在一种方法中，软件协同仿真平台被配置为产生电子系统的设计块的多个输入端口的值的第一时间序列，消耗电子系统的多个输出端口的值的第二时间序列并且生成用于传送第一和第二序列值的访问事务。软件协同仿真平台生成用于传送用于设计块的重新配置数据的多个重配置事务。 PLD被配置为实现通信块和控制块。通信块从软件协同仿真平台接收重新配置和访问事务，并且控制块响应于重新配置事务重新配置PLD的可编程逻辑和互连资源。响应于访问事务，控制块还控制设计块的仿真。

12. 发明授权

US08650517B1 Automatically documenting circuit designs 有权
标题翻译：自动记录电路设计
公开(公告)号：US08650517B1
公开(公告)日：2014-02-11
申请号：US12581631
申请日：2009-10-19
申请人： Arvind Sundararajan , Nabeel Shirazi , Jingzhao Ou , Chi Bun Chan
发明人： Arvind Sundararajan , Nabeel Shirazi , Jingzhao Ou , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Within a system comprising a processor and a memory, a method of automatically documenting a circuit design can include determining an assignment of a user comment entity (UCE) of a high level modeling system (HLMS) circuit design to an HLMS block of the HLMS circuit design, translating each HLMS block of the HLMS circuit design into a hardware description language (HDL) representation of the HLMS block, and for each HLMS block assigned a UCE, inserting within the HDL representation, by the processor, content of the UCE that is assigned to the HLMS block in the form of a comment. The HDL representations can be stored within the memory.
摘要翻译：在包括处理器和存储器的系统中，自动记录电路设计的方法可以包括确定高级建模系统（HLMS）电路设计的用户评论实体（UCE）对HLMS电路的HLMS块的分配将HLMS电路设计的每个HLMS块转换为HLMS块的硬件描述语言（HDL）表示，并且对于分配了UCE的每个HLMS块，由处理器在HDL表示内插入，将UCE的内容以注释的形式分配给HLMS块。 HDL表示可以存储在内存中。

13. 发明授权

US08620638B1 Method of performing a simulation of a design under test and a circuit for enabling testing of a circuit design 有权
标题翻译：执行被测设计的仿真的方法和用于实现电路设计测试的电路
公开(公告)号：US08620638B1
公开(公告)日：2013-12-31
申请号：US12335025
申请日：2008-12-15
申请人： Chi Bun Chan , Jingzhao Ou , Shay Ping Seng , Nabeel Shirazi
发明人： Chi Bun Chan , Jingzhao Ou , Shay Ping Seng , Nabeel Shirazi
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5022
摘要： A method of performing a simulation of a design under test is disclosed. The method comprises implementing an input block having an adjustable output width; coupling test data to the input block; generating an input signal comprising the test data for the design under test according to an input requirement for the design under test by way of the input block; implementing an output block having an adjustable input width for receiving data from an output of the design under test; and coupling the output of the design under test to the output block according to an output requirement of the design under test. A circuit for enabling testing of a circuit design implemented in an integrated circuit is also disclosed.
摘要翻译：公开了一种对被测设计进行仿真的方法。该方法包括实现具有可调输出宽度的输入块; 将测试数据耦合到输入块; 根据输入块的被测设计的输入要求，生成包含被测设计的测试数据的输入信号; 实现具有可调输入宽度的输出块，用于从被测设计的输出接收数据; 并根据被测设计的输出要求将被测设计的输出耦合到输出块。还公开了一种能够测试在集成电路中实现的电路设计的电路。

14. 发明授权

US08600722B1 Method and apparatus for providing program-based hardware co-simulation of a circuit design 有权
标题翻译：用于提供电路设计的基于程序的硬件协同仿真的方法和装置
公开(公告)号：US08600722B1
公开(公告)日：2013-12-03
申请号：US11805133
申请日：2007-05-22
申请人： Chi Bun Chan , Nabeel Shirazi , Shay Ping Seng , Haibing Ma
发明人： Chi Bun Chan , Nabeel Shirazi , Shay Ping Seng , Haibing Ma
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： A method and apparatus for providing a program-based hardware co-simulation of a circuit design are described. In one example, a circuit design is implemented for programmable logic to establish a design under test (DUT). A co-simulation model is programmatically generated using primitives defined by an application programming interface (API). The circuit design is simulated by configuring the programmable logic with the DUT and driving a co-simulation engine to communicate with the DUT via execution of the co-simulation model.
摘要翻译：描述了一种用于提供电路设计的基于程序的硬件协同仿真的方法和装置。在一个示例中，实现用于可编程逻辑以建立被测设计（DUT）的电路设计。使用由应用程序编程接口（API）定义的原语以编程方式生成协同仿真模型。通过使用DUT配置可编程逻辑来模拟电路设计，并通过执行协同仿真模型驱动协同仿真引擎与DUT进行通信。

15. 发明授权

US08417965B1 Method and circuit for secure definition and integration of cores 有权
标题翻译：核心的安全定义和集成的方法和电路
公开(公告)号：US08417965B1
公开(公告)日：2013-04-09
申请号：US12755760
申请日：2010-04-07
申请人： Arvind Sundararajan , Chi Bun Chan , Nabeel Shirazi
发明人： Arvind Sundararajan , Chi Bun Chan , Nabeel Shirazi
IPC分类号： G06F11/30 , G06F12/14 , G06F7/04 , G06F17/30 , G06F9/445 , H04L29/06 , H04L9/00 , H04L9/30 , H04K1/00 , H04N7/16
CPC分类号： G06F17/505 , G06F11/3664 , G06F17/5054 , H04L9/0825 , H04L9/0877 , H04L63/0478
摘要： An embodiment of the present invention provides a method and circuit for secure definition and integration of a core into a circuit design without exposing the core. In one embodiment, a core development package is obtained. The core development package includes an encrypted core and a decryption key of the encrypted core. The decryption key is encrypted with an asymmetric cipher. The encrypted core is transmitted from the design tool to a trusted platform module. The decryption key is decrypted with a private key of the asymmetric cipher. The encrypted core is decrypted within the trusted platform module. One or more design tool operations are performed using the decrypted core.
摘要翻译：本发明的一个实施例提供了一种用于将核心安全地定义和集成到电路设计中而不暴露核心的方法和电路。在一个实施例中，获得核心开发包。核心开发包包括加密核心和加密核心的解密密钥。解密密钥用非对称密码加密。加密核心从设计工具传输到可信平台模块。解密密钥用非对称密码的私钥解密。加密核心在可信平台模块内被解密。使用解密的核执行一个或多个设计工具操作。

16. 发明授权

US07590137B1 Parameterizable compact network processor for low-level communication with an integrated circuit 有权
标题翻译：可配置的紧凑型网络处理器，用于与集成电路进行低级通信
公开(公告)号：US07590137B1
公开(公告)日：2009-09-15
申请号：US11285708
申请日：2005-11-22
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
IPC分类号： H04J3/24
CPC分类号： G06F13/385 , G06F2213/3808
摘要： A network processor, disposed on an integrated circuit can include an ingress unit having a dual port block random access memory and an egress unit having a dual port block random access memory. The network processor further can include a network interface configured to write packetized data to the ingress unit and read packetized data from the egress unit as well as a coordination processor configured to coordinate movement of data between the network interface, the ingress unit, and the egress unit.
摘要翻译：设置在集成电路上的网络处理器可以包括具有双端口块随机存取存储器的入口单元和具有双端口块随机存取存储器的出口单元。网络处理器还可以包括被配置为将分组化数据写入入口单元并从出口单元读取分组化数据的网络接口以及配置为协调网络接口，入口单元和出口之间的数据移动的协调处理器单元。

17. 发明授权

US08219958B1 Creating evaluation hardware using a high level modeling system 有权
标题翻译：使用高级建模系统创建评估硬件
公开(公告)号：US08219958B1
公开(公告)日：2012-07-10
申请号：US12720563
申请日：2010-03-09
申请人： Arvind Sundararajan , Nabeel Shirazi
发明人： Arvind Sundararajan , Nabeel Shirazi
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G06F17/505 , G06F2217/66
摘要： Within a system comprising a processor and a memory, a method of creating evaluation hardware within an integrated circuit can include automatically inserting, by the processor, a disable circuit block into a circuit design. The method can also include automatically selecting a location within the circuit design to insert the disable circuit block, and/or inserting an unlock circuit block into the circuit design, wherein responsive to receiving an unlock code, the unlock circuit block overrides the disable circuit block. The method also can include storing, within the memory, the circuit design comprising the disable circuit block.
摘要翻译：在包括处理器和存储器的系统中，在集成电路内创建评估硬件的方法可以包括由处理器将禁用电路块自动插入到电路设计中。该方法还可以包括自动选择电路设计中的位置以插入禁用电路块，和/或将解锁电路块插入到电路设计中，其中响应于接收到解锁码，解锁电路块覆盖禁用电路块。该方法还可以包括在存储器内存储包括禁用电路块的电路设计。

18. 发明授权

US07346482B1 Shared memory for co-simulation 有权
标题翻译：共享内存共同模拟
公开(公告)号：US07346482B1
公开(公告)日：2008-03-18
申请号：US11075340
申请日：2005-03-08
申请人： Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi , Joshua Ian Stone
发明人： Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi , Joshua Ian Stone
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Co-simulation of a circuit design includes simulating a first subset of blocks of the circuit design on a software-based co-simulation platform, simulating a second subset of the blocks of the circuit design on a hardware-based co-simulation platform, and maintaining coherency for a memory block of the circuit design between a first representation of data in the memory block on the software-based co-simulation platform and a second representation of the data in the memory block on the hardware-based co-simulation platform. Coherency is maintained by managing mutually exclusive access to the memory block from the first subset of blocks and the second subset of blocks.
摘要翻译：电路设计的协同仿真包括在基于软件的协同仿真平台上模拟电路设计的块的第一子集，在基于硬件的协同仿真平台上模拟电路设计的块的第二子集，以及在基于软件的协同仿真平台的存储器块中的数据的第一表示和基于硬件的协同仿真平台的存储器块中的数据的第二表示之间维持电路设计的存储器块的一致性。通过管理来自块的第一子集和块的第二子集的对存储器块的互斥访问来维持一致性。

19. 发明授权

US07343572B1 Vector interface to shared memory in simulating a circuit design 有权
标题翻译：模拟电路设计的共享内存的矢量接口
公开(公告)号：US07343572B1
公开(公告)日：2008-03-11
申请号：US11096024
申请日：2005-03-31
申请人： Joshua Ian Stone , Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi
发明人： Joshua Ian Stone , Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A first block, a second block, a shared memory, and a third block are generated in a circuit design in response to user input control. The first block is coupled to the second block, the second block is coupled to the shared memory, and the shared memory is coupled to the third block in response to user input control. During one cycle of a simulation, the second block, in response to the first block, accesses a set of scalar values in the shared memory using scalar accesses. During one cycle of the simulation, the set of scalar values is transferred between the second block and the first block. During the simulation, the shared memory is accessed by the third block using scalar accesses.
摘要翻译：响应于用户输入控制，在电路设计中产生第一块，第二块，共享存储器和第三块。第一块耦合到第二块，第二块耦合到共享存储器，并且响应于用户输入控制，共享存储器耦合到第三块。在仿真的一个周期期间，响应于第一个块，第二个块使用标量访问访问共享存储器中的一组标量值。在模拟的一个周期期间，标量值集合在第二块和第一块之间传送。在仿真期间，使用标量访问由第三块访问共享存储器。

20. 发明授权

US07003751B1 Specification of the hierarchy, connectivity, and graphical representation of a circuit design 有权
标题翻译：电路设计的层次结构，连接性和图形表示的规范
公开(公告)号：US07003751B1
公开(公告)日：2006-02-21
申请号：US10340498
申请日：2003-01-10
申请人： Jeffrey D. Stroomer , Roger B. Milne , Jonathan B. Ballagh , Haibing Ma , L. James Hwang , Nabeel Shirazi
发明人： Jeffrey D. Stroomer , Roger B. Milne , Jonathan B. Ballagh , Haibing Ma , L. James Hwang , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Method and apparatus for creating a circuit design. An object-oriented program instantiates a plurality of objects that model a circuit design. The objects have hierarchy attributes, connectivity attributes, and display attributes that describe a plurality of modules. The hierarchy attributes define parent-child relationships between modules, the connectivity attributes define input-output connections between modules, and the display attributes define a layout of the modules for viewing. Each of the objects has an associated method for generating a design specification in a selected format. When the program is executed, the design specification is generated from the set of objects. Depending on the capabilities of the available tools, the modules and logic elements are displayed in accordance with the display attributes either from the object-oriented program or from the design specification.
摘要翻译：用于创建电路设计的方法和装置。面向对象的程序实例化建模电路设计的多个对象。对象具有描述多个模块的层次属性，连接属性和显示属性。层次结构属性定义模块之间的父子关系，连接属性定义模块之间的输入输出连接，显示属性定义模块的布局以供查看。每个对象具有用于以所选格式生成设计规范的关联方法。当执行程序时，设计规范是从对象集合生成的。根据可用工具的功能，根据面向对象程序或设计规范的显示属性显示模块和逻辑元素。

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