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11. 发明授权

US07376544B1 Vector transfer during co-simulation 有权
标题翻译：矢量传输在协同仿真期间
公开(公告)号：US07376544B1
公开(公告)日：2008-05-20
申请号：US10777419
申请日：2004-02-12
申请人： Christopher H. Dick , Nabeel Shirazi , Roger B. Milne , Jeffrey D. Stroomer , Jonathan B. Ballagh
发明人： Christopher H. Dick , Nabeel Shirazi , Roger B. Milne , Jeffrey D. Stroomer , Jonathan B. Ballagh
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Various embodiments are disclosed for transferring data between blocks in a design during simulation. Operation of at least one high-level block in the design is simulated in a high-level modeling system (HLMS). A hardware-implemented block in the design is co-simulated on a hardware simulation platform. A first vector of data received by a co-simulation block is transferred to the simulated hardware-implemented block via a transfer function.
摘要翻译：公开了用于在模拟期间在设计中的块之间传送数据的各种实施例。在高级建模系统（HLMS）中模拟设计中至少一个高级块的操作。设计中的硬件实现块在硬件仿真平台上共同模拟。由模拟块接收的第一数据矢量通过传递函数被传送到模拟硬件实现的块。

12. 发明授权

US07346481B1 Hardware co-simulation breakpoints in a high-level modeling system 有权
标题翻译：硬件共模拟断点在高级建模系统中
公开(公告)号：US07346481B1
公开(公告)日：2008-03-18
申请号：US10930619
申请日：2004-08-31
申请人： Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer
发明人： Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5022 , G06F2217/62 , G06F2217/86
摘要： Various approaches for controlling simulation of an electronic system are disclosed. In one approach, at least one breakpoint block is instantiated in a high-level design. The breakpoint block has an associated breakpoint condition driven by at least one signal of the design, and the design further includes at least one simulation block and at least one co-simulation block. The simulation block is simulated on a software-based simulation platform, and the co-simulation block and the breakpoint block are co-simulated on a hardware-based co-simulation platform. Advancement of a clock signal to the co-simulation block on the hardware-based co-simulation platform is inhibited in response to satisfaction of the breakpoint condition. After inhibiting the clock signal, advancement of steps of the clock signal is controlled on the co-simulation platform in one of a plurality of user-selectable clock advancement modes.
摘要翻译：公开了用于控制电子系统的仿真的各种方法。在一种方法中，至少一个断点块在高级设计中被实例化。断点块具有由设计的至少一个信号驱动的相关联的断点条件，并且该设计还包括至少一个模拟块和至少一个协同模拟块。模拟块在基于软件的仿真平台上进行仿真，并且在基于硬件的协同仿真平台上共同模拟了共模拟块和断点块。响应于断点条件的满足，抑制了基于硬件的协同仿真平台上的协同仿真块的时钟信号的进展。在禁止时钟信号之后，以多个用户可选择的时钟提前模式之一在协同仿真平台上控制时钟信号的步长的前进。

13. 发明授权

US07546572B1 Shared memory interface in a programmable logic device using partial reconfiguration 有权
标题翻译：使用部分重新配置的可编程逻辑器件中的共享存储器接口
公开(公告)号：US07546572B1
公开(公告)日：2009-06-09
申请号：US11230879
申请日：2005-09-20
申请人： Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer
发明人： Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer
IPC分类号： H03K17/693
CPC分类号： H03K19/17756 , H03K19/17732 , H03K19/1776
摘要： Partial reconfiguration of a programmable logic device is used in combination with a shared memory block for communicating between two blocks of an electronic circuit design. In one embodiment, a shared memory is implemented on RAM resources of a field programmable gate array (FPGA), and a first design block implemented in resources of the FPGA is coupled to the shared memory. A second design block is also coupled to the shared memory. In response to a write request by the second design block, a process determines the RAM resources of the FPGA that correspond to the shared memory address in the write request. A configuration bitstream is generated to include configuration data for partial reconfiguration of the FPGA with the data from the write request at the appropriate RAM resources. The FPGA is partially reconfigured with the configuration bitstream via a configuration port of the FPGA.
摘要翻译：可编程逻辑器件的部分重新配置与用于在电子电路设计的两个块之间进行通信的共享存储器块结合使用。在一个实施例中，在现场可编程门阵列（FPGA）的RAM资源上实现共享存储器，并且在FPGA的资源中实现的第一设计块耦合到共享存储器。第二设计块也耦合到共享存储器。响应于第二设计块的写请求，处理确定与写请求中的共享存储器地址相对应的FPGA的RAM资源。生成配置比特流以包括用于使用来自写入请求的数据在适当的RAM资源处对FPGA进行部分重新配置的配置数据。 FPGA通过FPGA的配置端口部分配置配置比特流。

14. 发明授权

US07433813B1 Embedding a co-simulated hardware object in an event-driven simulator 有权
标题翻译：在事件驱动的模拟器中嵌入一个共同模拟的硬件对象
公开(公告)号：US07433813B1
公开(公告)日：2008-10-07
申请号：US10850178
申请日：2004-05-20
申请人： Jonathan B. Ballagh , L. James Hwang , Roger B. Milne , Nabeel Shirazi
发明人： Jonathan B. Ballagh , L. James Hwang , Roger B. Milne , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Various approaches for embedding a hardware object in an event-driven simulator are disclosed. The various approaches involve generating an HDL proxy component having an HDL definition of each port of the hardware object and respective event handler functions associated with input ports of the HDL proxy component. The event handler functions are responsive to simulation events appearing on the input ports. A configuration bitstream is generated for implementing the hardware object on a programmable logic circuit, and a first object is generated to contain configuration parameter values indicating characteristics of the ports and a location of the configuration bitstream. A second object is generated and is configured to initiate configuration of the programmable logic circuit with the configuration bitstream. The second object further provides input data to and receives output data from the programmable logic circuit.
摘要翻译：公开了将硬件对象嵌入到事件驱动模拟器中的各种方法。各种方法涉及生成具有硬件对象的每个端口的HDL定义的HDL代理组件以及与HDL代理组件的输入端口相关联的相应事件处理程序功能。事件处理函数响应出现在输入端口上的模拟事件。生成用于在可编程逻辑电路上实现硬件对象的配置比特流，并且生成第一对象以包含指示端口的特性和配置比特流的位置的配置参数值。产生第二个目标，并且被配置为启动具有配置比特流的可编程逻辑电路的配置。第二个目的还提供输入数据并从可编程逻辑电路接收输出数据。

15. 发明授权

US07383478B1 Wireless dynamic boundary-scan topologies for field 有权
标题翻译：无线动态边界扫描拓扑领域
公开(公告)号：US07383478B1
公开(公告)日：2008-06-03
申请号：US11185118
申请日：2005-07-20
申请人： Jonathan B. Ballagh , Alexander Carreira , L. James Hwang , Roger B. Milne , Shay Ping Seng , Nabeel Shirazi
发明人： Jonathan B. Ballagh , Alexander Carreira , L. James Hwang , Roger B. Milne , Shay Ping Seng , Nabeel Shirazi
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/3025 , G01R31/318572 , H04W4/18 , H04W24/00 , H04W92/00
摘要： A programmable logic device (PLD) with a JTAG port, such as an FPGA, is provided with a wireless JTAG adapter to enable wireless communications. Multiple PLDs connected with wireless-to-JTAG adapters can be wirelessly linked in a network to form a large boundary-scan chain serial interface. To communicate with the PLDs having a wireless JTAG port, a host PC running application software is also equipped with a wireless transceiver.
摘要翻译：具有JTAG端口（例如FPGA）的可编程逻辑器件（PLD）提供有无线JTAG适配器以实现无线通信。与无线到JTAG适配器连接的多个PLD可以在网络中无线链接以形成大型边界扫描链串行接口。为了与具有无线JTAG端口的PLD通信，运行应用软件的主机PC还配备有无线收发器。

16. 发明授权

US07203632B2 HDL co-simulation in a high-level modeling system 有权
标题翻译： HDL在高级建模系统中的共模拟
公开(公告)号：US07203632B2
公开(公告)日：2007-04-10
申请号：US10389161
申请日：2003-03-14
申请人： Roger B. Milne , L. James Hwang , Jeffrey D. Stroomer , Nabeel Shirazi , Haibing Ma , Jonathan B. Ballagh
发明人： Roger B. Milne , L. James Hwang , Jeffrey D. Stroomer , Nabeel Shirazi , Haibing Ma , Jonathan B. Ballagh
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.
摘要翻译：用于模拟包括高级组件和HDL组件的电路设计操作的方法和装置。设计的高级组件在高级建模系统（HLMS）中进行模拟，并且使用HDL模拟器来模拟设计的HDL组件。将数据值从HLMS的数据类型转换为与HDL模拟器兼容的逻辑向量，以将每个数据值输入到HDL模拟器，并且将逻辑向量从HDL模拟器转换为数据类型的数据值与HDL模拟器的每个逻辑矢量输出的HLMS兼容。根据HLMS事件的时间和HDL组件的最大响应时间，事件被安排输入到HDL模拟器。

17. 发明授权

US09141255B2 Mosaic generation from user-created content 有权
标题翻译：用户创建内容的马赛克生成
公开(公告)号：US09141255B2
公开(公告)日：2015-09-22
申请号：US12974346
申请日：2010-12-21
申请人： Jeffrey D. Stroomer , Jonathan B. Ballagh , Roger B. Milne , Jeffrey C. Ward , Krista M. Marks , Thomas E. Fischaber
发明人： Jeffrey D. Stroomer , Jonathan B. Ballagh , Roger B. Milne , Jeffrey C. Ward , Krista M. Marks , Thomas E. Fischaber
IPC分类号： G06F3/00 , G06F5/00 , G06F3/0481
CPC分类号： G06F3/0481
摘要： Techniques for creating a mosaic using user-created content on a content sharing site. Embodiments of the invention may provide an interface on the content sharing site to allow users to create content. Embodiments may then determine a suitability value between the user-created content and portions of a mosaic, and insert the user-created content into a particular portion of the mosaic based on the determined suitability value for the particular portion.
摘要翻译：在内容共享网站上使用用户创建的内容创建马赛克的技术。本发明的实施例可以提供内容共享站点上的接口，以允许用户创建内容。实施例然后可以确定用户创建的内容和马赛克的部分之间的适合性值，并且基于所确定的特定部分的适用性值将用户创建的内容插入到马赛克的特定部分中。

18. 发明授权

US07797677B1 Using scripts for netlisting in a high-level modeling system 有权
标题翻译：在高级建模系统中使用脚本进行网页列表
公开(公告)号：US07797677B1
公开(公告)日：2010-09-14
申请号：US11268801
申请日：2005-11-08
申请人： Jonathan B. Ballagh , Sean A. Kelly , Roger B. Milne , Shay Ping Seng , Jeffrey D. Stroomer
发明人： Jonathan B. Ballagh , Sean A. Kelly , Roger B. Milne , Shay Ping Seng , Jeffrey D. Stroomer
IPC分类号： G06F9/44
CPC分类号： G06F9/543 , G06F9/541 , G06F17/5054
摘要： A method of passing data among modules of a heterogeneous software system can include identifying a scripted function to be executed within the heterogeneous software system and building a wrapper script by embedding a call to the scripted function and an XTable object associated with the scripted function within the wrapper script. The method further can include executing the wrapper script thereby causing the scripted function to execute and receiving a result from execution of the scripted function.
摘要翻译：在异构软件系统的模块之间传递数据的方法可以包括识别要在异构软件系统内执行的脚本化功能，以及通过嵌入对脚本化功能的调用和与脚本化功能相关联的XTable对象来构建包装器脚本包装脚本该方法还可以包括执行包装器脚本，从而使脚本化功能执行并从脚本化功能的执行接收结果。

19. 发明授权

US07194705B1 Simulation of integrated circuitry within a high-level modeling system using hardware description language circuit descriptions 有权
标题翻译：在使用硬件描述语言电路描述的高级建模系统中对集成电路进行仿真
公开(公告)号：US07194705B1
公开(公告)日：2007-03-20
申请号：US10388692
申请日：2003-03-14
申请人： Kumar Deepak , L. James Hwang , Singh Vinay Jitendra , Haibing Ma , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer , Jimmy Zhenming Wang
发明人： Kumar Deepak , L. James Hwang , Singh Vinay Jitendra , Haibing Ma , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer , Jimmy Zhenming Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Method, apparatus, and computer readable medium for simulating an integrated circuit within a modeling system using one or more circuit description language representations of circuitry is described. By example, a circuit description language representation of the one or more circuit description language representations of circuitry is translated into a program language circuit description. A first simulation process is executed and input data is obtained therefrom. A second simulation process is executed with the input data as parametric input to produce output data, the second simulation process being derived from the program language circuit description. The output data produce by the second simulation process is provided to the first simulation process.
摘要翻译：描述了使用电路的一个或多个电路描述语言表示来模拟建模系统内的集成电路的方法，装置和计算机可读介质。例如，电路的一个或多个电路描述语言表示的电路描述语言表示被转换成程序语言电路描述。执行第一模拟处理并从其获得输入数据。以输入数据作为参数输入来执行第二模拟处理以产生输出数据，第二模拟处理从程序语言电路描述导出。通过第二次模拟处理产生的输出数据被提供给第一个仿真过程。

20. 发明申请

US20120079390A1 Method and Apparatus of Graphical Object Selection in a Web Browser 有权
标题翻译： Web浏览器中图形对象选择的方法和装置
公开(公告)号：US20120079390A1
公开(公告)日：2012-03-29
申请号：US13308191
申请日：2011-11-30
申请人： Jonathan B. Ballagh , Thomas E. Fischaber , Roger B. Milne , Krista M. Marks
发明人： Jonathan B. Ballagh , Thomas E. Fischaber , Roger B. Milne , Krista M. Marks
IPC分类号： G06F3/048
CPC分类号： G09G5/14 , G06F3/0481 , G06F2203/04804 , G06T11/00 , G06T11/60 , G06T15/503 , G09G2340/12
摘要： Various approaches for selection of graphical objects in a web browser-based application are described. In one approach, a selection overlay is stored in a web document. The selection overlay encompasses a plurality of user-selectable graphical objects in the web document occupies a highest position in layers of graphical objects in the web document and includes a plurality of selection regions. Each selection region is respectively associated with one of the plurality of graphical objects and defines a region of selectability for the associated graphical object. In response to the web browser-based application detecting entry of a user-directed pointer into one of the selection regions in the selection overlay, the graphical object associated with the one selection region is selected for user manipulation and displayed.
摘要翻译：描述了用于在基于web浏览器的应用中选择图形对象的各种方法。在一种方法中，选择覆盖存储在web文档中。所述选择覆盖层包括所述web文档中的多个用户可选图形对象占据所述web文档中的图形对象层中的最高位置，并且包括多个选择区域。每个选择区域分别与多个图形对象中的一个相关联并且定义关联的图形对象的可选择性区域。响应于基于web浏览器的应用程序检测用户指向的指针进入选择覆盖中的一个选择区域，选择与一个选择区域相关联的图形对象用于用户操纵和显示。

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