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11. 发明申请

US20110302544A1 POST-PLACEMENT CELL SHIFTING 失效
标题翻译：后置放电细胞移位
公开(公告)号：US20110302544A1
公开(公告)日：2011-12-08
申请号：US12796550
申请日：2010-06-08
申请人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Lakshmi N. Reddy , Jarrod A. Roy , Taraneh Taghavi , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块。扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。扩张器也可能使这些细胞膨胀并合法化。

12. 发明申请

US20110302545A1 DETAILED ROUTABILITY BY CELL PLACEMENT 有权
标题翻译：细节放置的详细的不可靠性
公开(公告)号：US20110302545A1
公开(公告)日：2011-12-08
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

13. 发明授权

US09524363B2 Element placement in circuit design based on preferred location 有权
标题翻译：基于优选位置的电路设计元素放置
公开(公告)号：US09524363B2
公开(公告)日：2016-12-20
申请号：US13485828
申请日：2012-05-31
申请人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5081
摘要： An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.
摘要翻译：改进的电路设计系统可以包括计算机处理器，以通过物理合成来执行电路的放置。该系统还可以包括控制器，用于计算电路的至少一个选定元件的优选位置，并且计算每个选定元件的放置约束。该系统可以进一步包括通过用放置约束执行另一轮物理合成而产生的电路的更新设计。

14. 发明授权

US06671867B2 Analytical constraint generation for cut-based global placement 有权
公开(公告)号：US06671867B2
公开(公告)日：2003-12-30
申请号：US10121877
申请日：2002-04-11
申请人： Charles J. Alpert , Gi-Joon Nam , Paul G. Villarrubia
发明人： Charles J. Alpert , Gi-Joon Nam , Paul G. Villarrubia
IPC分类号： G06F945
CPC分类号： G06F17/5072
摘要： A method of designing the layout of an integrated circuit (IC) by deriving an analytical constraint for a cut-based placement partitioner using analytical optimization, and placing cells on the IC with the cut-based placement partitioner using the analytical constraint. Quadratic optimization may be used to determine a desired ratio of a cell area of a given partition to a total cell area (the balance parameter), and placing may be performed using multilevel bisection partitioning constrained by the balance parameter. This implementation may include a determination of an aspect ratio for an entire partitioning region of the integrated circuit, and a “center-of-mass” coordinate of the cells based on the quadratic optimization, which are then used to define a placement rectangle having the same aspect ratio, and centered on the center-of-mass coordinate. This placement rectangle is used to derive the balance parameter. The placement rectangle has a total area equal to a total moveable cell area, and the balance parameter is computed by calculating the ratio of a left portion of the placement rectangle which lies in the left partition to the total area of the placement rectangle. The multilevel partitioner then places a proportionate number of the cells in the left partition based on the balance parameter.

15. 发明申请

US20120284733A1 Scheduling for Parallel Processing of Regionally-Constrained Placement Problem 有权
标题翻译：并行处理区域约束布局的调度问题
公开(公告)号：US20120284733A1
公开(公告)日：2012-11-08
申请号：US13550957
申请日：2012-07-17
申请人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
发明人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
IPC分类号： G06F9/46
CPC分类号： G06F17/50 , G06F9/5066
摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.
摘要翻译：区域约束对象放置的并行处理调度在不同的平衡方案之间进行选择。对于少量的移动端口，通过平衡可放置对象来分配计算。对于每次移动的少量对象，通过平衡移动端口分配计算。如果每次移动都有大量的移动和对象，则处理器之间的对象和移动对象都是平衡的。对于对象平衡，移动端口被分配给一个处理器，直到处理器的摊销对象数量超过理想数量以上的第一个限制，或者下一个移动端口将提高超过第二个更大限制的对象数量。对于对象和移动平衡，移动排列按降序排列，然后按顺序分配给主机处理器，连续回合，同时在每轮之后反转处理器顺序。本发明提供多项式时间的时间表，同时保持高质量的结果。

16. 发明授权

US08578315B2 Scheduling for parallel processing of regionally-constrained placement problem 有权
公开(公告)号：US08578315B2
公开(公告)日：2013-11-05
申请号：US13550957
申请日：2012-07-17
申请人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
发明人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F9/5066
摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.

17. 发明申请

US20120297355A1 WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN 审中-公开
标题翻译：电路设计中的创新和保存
公开(公告)号：US20120297355A1
公开(公告)日：2012-11-22
申请号：US13112098
申请日：2011-05-20
申请人： Charles Jay Alpert , Gi-Joon Nam , Shyam Ramji , Jarrod Alexander Roy , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles Jay Alpert , Gi-Joon Nam , Shyam Ramji , Jarrod Alexander Roy , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method, system, and computer program product for whitespace creation and preservation in the design of an integrated circuit (IC) are provided in the illustrative embodiments. A first estimate is formed by estimating an amount of whitespace that is needed to reduce a congestion value of a congested area of the design to a threshold value. A set of virtual filler cells is added to the congested area, wherein adding the set of virtual filler cells does not add actual whitespace cells to the congested area but reduces the congested area by at least the first estimate. A virtual filler cell in the set of virtual filler cells is replaced with a corresponding real filler cell. A determination is made whether the design has improved. A final placement solution is created when the design has not improved.
摘要翻译：在说明性实施例中提供了用于集成电路（IC）设计中的空白创建和保存的方法，系统和计算机程序产品。通过估计将设计的拥塞区域的拥塞值减少到阈值所需的空白量来形成第一估计。将一组虚拟填充单元添加到拥塞区域，其中添加虚拟填充单元组不会向拥塞区域添加实际空白单元，而是至少通过第一估计减少拥塞区域。虚拟填充单元组中的虚拟填充单元被替换为相应的真实填充单元。确定设计是否改进。当设计没有改进时，创建最终的布局解决方案。

18. 发明申请

US20100192155A1 SCHEDULING FOR PARALLEL PROCESSING OF REGIONALLY-CONSTRAINED PLACEMENT PROBLEM 有权
标题翻译：并行处理区域性约束放置问题的调度
公开(公告)号：US20100192155A1
公开(公告)日：2010-07-29
申请号：US12359369
申请日：2009-01-26
申请人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
发明人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
IPC分类号： G06F9/50 , G06F9/46
CPC分类号： G06F17/50 , G06F9/5066
摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.
摘要翻译：区域约束对象放置的并行处理调度在不同的平衡方案之间进行选择。对于少量的移动端口，通过平衡可放置对象来分配计算。对于每次移动的少量对象，通过平衡移动端口分配计算。如果每次移动都有大量的移动和对象，则处理器之间的对象和移动对象都是平衡的。对于对象平衡，移动端口被分配给一个处理器，直到处理器的对象的摊销数量超过理想数量以上的第一个限制，或者下一个移动端口将提高超过第二个更大限制的对象数量。对于对象和移动平衡，移动排列按降序排列，然后按顺序分配给主机处理器，连续回合，同时在每轮之后反转处理器顺序。本发明提供多项式时间的时间表，同时保持高质量的结果。

19. 发明授权

US08245173B2 Scheduling for parallel processing of regionally-constrained placement problem 有权
标题翻译：并行处理区域约束放置问题的调度
公开(公告)号：US08245173B2
公开(公告)日：2012-08-14
申请号：US12359369
申请日：2009-01-26
申请人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
发明人： Gi-Joon Nam , Shyam Ramji , Taraneh Taghavi , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F9/5066
摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.
摘要翻译：区域约束对象放置的并行处理调度在不同的平衡方案之间进行选择。对于少量的移动端口，通过平衡可放置对象来分配计算。对于每次移动的少量对象，通过平衡移动端口分配计算。如果每次移动都有大量的移动和对象，则处理器之间的对象和移动对象都是平衡的。对于对象平衡，移动端口被分配给一个处理器，直到处理器的对象的摊销数量超过理想数量以上的第一个限制，或者下一个移动端口将提高超过第二个更大限制的对象数量。对于对象和移动平衡，移动排列按降序排列，然后按顺序分配给主机处理器，连续回合，同时在每轮之后反转处理器顺序。本发明提供多项式时间的时间表，同时保持高质量的结果。

20. 发明申请

US20140007036A1 SEPARATE REFINEMENT OF LOCAL WIRELENGTH AND LOCAL MODULE DENSITY IN INTERMEDIATE PLACEMENT OF AN INTEGRATED CIRCUIT DESIGN 有权
标题翻译：集成电路设计的中间位置的局部线性和局部模块密度的单独修正
公开(公告)号：US20140007036A1
公开(公告)日：2014-01-02
申请号：US13539440
申请日：2012-06-30
申请人： Charles J. Alpert , Myung-Chul Kim , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
发明人： Charles J. Alpert , Myung-Chul Kim , Gi-Joon Nam , Shyam Ramji , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： After a global placement phase of physical design of an integrated circuit, a data processing system iteratively refines local placement of a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and separately refines local wirelength for the plurality of modules in individual subareas among a plurality of subareas of the die area. The data processing system thereafter performs detailed placement of modules in the plurality of subareas.
摘要翻译：在集成电路的物理设计的全局放置阶段之后，数据处理系统基于多个模块的密度迭代地将包括该集成电路的多个模块的本地放置精细化，并单独地对多个模块中的局部线长进行精细化在模具区域的多个子区域中的各个子区域中的模块。此后，数据处理系统在多个子区域中执行模块的详细布置。

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