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11. 发明授权

US5533020A ATM cell scheduler 失效
标题翻译： ATM信元调度器
公开(公告)号：US5533020A
公开(公告)日：1996-07-02
申请号：US332160
申请日：1994-10-31
申请人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Baiju V. Patel , Kevin G. Plotz , Frank A. Schaffa , Marc H. Willebeek-LeMair
发明人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Baiju V. Patel , Kevin G. Plotz , Frank A. Schaffa , Marc H. Willebeek-LeMair
IPC分类号： G06F13/00 , H04L12/56 , H04L29/06 , H04L29/08 , H04Q3/00 , H04Q11/04
CPC分类号： H04L12/5602 , H04Q11/0478 , H04L2012/5635 , H04L2012/5651 , H04L2012/5672 , H04L2012/5679
摘要： A method and apparatus for scheduling the transmission of a number of data streams over a common communications link, where each of the data streams conforms to a corresponding set of flow control parameters. Each of the data streams to be transmitted on the communications link is stored in a corresponding queue. The status of each queue is maintained, and a target transmission time is calculated for each queue. Signals are then generated for each queue at a time at least after the target transmission time, and these signals are used to indicate to a corresponding queue that is can transmit a cell on the link. Upon reception of a corresponding signal, a queue then transmits at least one cell onto the communications link.
摘要翻译：一种用于通过公共通信链路调度多个数据流的传输的方法和装置，其中每个数据流符合对应的一组流量控制参数。要在通信链路上发送的每个数据流都存储在相应的队列中。维护每个队列的状态，并计算每个队列的目标传输时间。然后至少在目标传输时间之后，每个队列生成信号，并且这些信号用于指示可以在链路上传送单元的相应队列。在接收到对应信号时，队列随后将至少一个小区发送到通信链路上。

12. 发明授权

US5287527A Logical signal output drivers for integrated circuit interconnection 失效
标题翻译：用于集成电路互连的逻辑信号输出驱动器
公开(公告)号：US5287527A
公开(公告)日：1994-02-15
申请号：US997380
申请日：1992-12-28
申请人： Gary S. Delp , Brian A. Schuelke
发明人： Gary S. Delp , Brian A. Schuelke
IPC分类号： H03K17/693 , G06F12/06 , G11C7/10 , G11C8/12 , G11C11/401 , H03K19/003 , H03K19/0175 , G11C8/00
CPC分类号： G11C7/1051 , G11C8/12
摘要： Disclosed is a logic output signal generating integrated circuit having a plurality of output drivers connected in parallel between a power bus and a ground bus. Each output driver has a pull up device disposed between the power bus and an output terminal and a pull down device disposed between the output terminal and the ground bus. Output drivers are paired for the reception of control signals. Control gates to the pull up device and the pull down device for one output driver in a pair is connected to receive an on-chip logic signal. The second output driver of the pair has the complement of that logic signal applied to the control gates of its pull up and pull down devices. An inverter operates on the logic signal to provide the complement. The load is divided between the output drivers for the true signals and those for the complementary signals.
摘要翻译：公开了一种逻辑输出信号产生集成电路，其具有并联连接在电源总线和接地总线之间的多个输出驱动器。每个输出驱动器具有设置在电源总线和输出端子之间的上拉装置和设置在输出端子和接地总线之间的下拉装置。输出驱动器配对用于接收控制信号。一对输出驱动器的上拉装置和下拉装置的控制栅极被连接以接收片上逻辑信号。该对的第二输出驱动器具有施加到其上拉和下拉器件的控制栅极的该逻辑信号的补码。逆变器对逻辑信号进行操作以提供补码。负载在真实信号的输出驱动器和互补信号的输出驱动器之间划分。

13. 发明申请

US20100031222A1 BASE PLATFORMS WITH COMBINED ASIC AND FPGA FEATURES AND PROCESS OF USING THE SAME 失效
标题翻译：具有组合ASIC和FPGA特性的基站平台以及使用它们的过程
公开(公告)号：US20100031222A1
公开(公告)日：2010-02-04
申请号：US12576775
申请日：2009-10-09
申请人： Gary S. Delp , George Wayne Nation
发明人： Gary S. Delp , George Wayne Nation
IPC分类号： G06F17/50 , H03K19/173
CPC分类号： G06F17/505 , G06F17/5054
摘要： A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.
摘要翻译：公开了一种用于配置具有ASIC和FPGA模块以执行多个功能的基础平台的过程。对电路的验证RTL硬件描述进行映射和注释，以识别存储器可编程功能。存储器可编程功能被分组以分配给FPGA模块。非存储器可编程功能被合成到ASIC模块，并且存储器可编程功能被合成到FPGA模块。完成放置，信号路由和边界定时关闭，并通过添加金属化层来配置ASIC模块并创建固件存储器来配置FPGA模块来配置平台。 FPGA模块中的过度供应功能允许逻辑功能的后制造改变。

14. 发明申请

US20080248612A1 ASYMMETRIC ALIGNMENT OF SUBSTRATE INTERCONNECT TO SEMICONDUCTOR DIE 有权
标题翻译：基板与半导体芯片的非对称对准
公开(公告)号：US20080248612A1
公开(公告)日：2008-10-09
申请号：US12139185
申请日：2008-06-13
申请人： Gary S. Delp
发明人： Gary S. Delp
IPC分类号： H01L21/00
CPC分类号： H01L23/5386 , H01L24/81 , H01L25/0655 , H01L2224/24226 , H01L2224/81801 , H01L2224/82 , H01L2224/85 , H01L2224/86 , H01L2924/14 , H01L2924/00
摘要： An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.
摘要翻译：一种装置包括第一半导体管芯和至少一个另外的半导体管芯。衬底附接到第一裸片和另一裸片，并且具有将第一裸片上的触点与另一裸片上的相应触点互连的电互连图案。互连图案的特征在基板上具有相对于第一裸片上的触点的位置具有比在另一裸片上的触点的位置更小的公差的位置。

15. 发明授权

US07352748B1 Updating of routing data in a network element 有权
标题翻译：更新网络元素中的路由数据
公开(公告)号：US07352748B1
公开(公告)日：2008-04-01
申请号：US10291999
申请日：2002-11-12
申请人： Ranjit Rozario , Gary S. Delp
发明人： Ranjit Rozario , Gary S. Delp
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/00 , H04L12/4625 , H04L45/60 , H04L45/7453
摘要： In one embodiment, an apparatus comprises a logic coupled to receive a number of data packets. The logic comprises an execution unit to generate a request for routing data for a data packet of the number of data packets. The logic also includes a memory lookup engine coupled to the execution unit and a local memory. The local memory is to store routing data for the number of data packets. The memory lookup engine is to receive the request and to update the local memory upon determining that the routing data for the data packet is not found in the local memory. Additionally, the logic includes a communication logic coupled to the memory lookup engine. The communication logic is to transmit an update message to a remote logic. The update message is to cause the remote logic to update a remote memory, wherein the update message is transmitted based on a low priority update upon determining that a buffer for update messages of the remote memory is full when the local memory is updated.
摘要翻译：在一个实施例中，一种装置包括耦合以接收多个数据分组的逻辑。该逻辑包括一个执行单元，用于产生数据包数目的数据包路由数据的请求。逻辑还包括耦合到执行单元和本地存储器的存储器查找引擎。本地存储器是存储数据包数量的路由数据。存储器查找引擎在确定在本地存储器中没有发现数据分组的路由数据时，接收请求并更新本地存储器。此外，逻辑包括耦合到存储器查找引擎的通信逻辑。通信逻辑是向远程逻辑发送更新消息。所述更新消息是使所述远程逻辑更新远程存储器，其中，当更新所述本地存储器时，在确定所述远程存储器的更新消息的缓冲器已满之后，基于低优先级更新发送所述更新消息。

16. 发明授权

US5634015A Generic high bandwidth adapter providing data communications between diverse communication networks and computer system 失效
标题翻译：通用高带宽适配器提供不同通信网络和计算机系统之间的数据通信
公开(公告)号：US5634015A
公开(公告)日：1997-05-27
申请号：US317894
申请日：1994-10-04
申请人： Paul Chang , Gary S. Delp , Hanafy E.-S. Meleis , Rafael M. Montalvo , David I. Seidman , Ahmed N.-E.-D. Tantawy , Dominick A. Zumbo
发明人： Paul Chang , Gary S. Delp , Hanafy E.-S. Meleis , Rafael M. Montalvo , David I. Seidman , Ahmed N.-E.-D. Tantawy , Dominick A. Zumbo
IPC分类号： G06F13/00 , G06F5/06 , G06F13/12 , G06F13/38 , H04L12/18 , H04L12/56 , H04L29/10
CPC分类号： H04L49/9026 , G06F13/128 , G06F13/387 , G06F5/06 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9047 , H04L12/18 , H04L49/205 , H04L49/3027 , H04L49/351
摘要： A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. A packet memory stores data packets arriving at a plurality of generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. The generic adapter manager prepares future response to anticipated requests for communications services which are functions of the current requests for communication services, such as preparing a response for an anticipated request for a next buffer by a current request for a receipt of data. The generic adapter manager stores the future responses at specified addresses in memory which can be read by a requester. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.
摘要翻译：通用高带宽适配器，为总线，通道，处理器，交换结构和/或通信网络之间的数据通信提供统一架构。数据由可变长度的数据流分组携带，每个分组包括用于调停信息交换的通信协议所需的报头控制信息部分，通常是要传送的数据的数据部分。分组存储器存储到达多个通用适配器输入/输出端口的数据分组。分组存储器被分割成多个缓冲器，并且每个数据分组根据其长度的要求存储在一个或多个缓冲器中。提供通用适配器管理器，用于执行和同步通用适配器管理功能，包括通过在缓冲器中组织数据分组来实现分组存储器中的数据结构，以及将数据分组组织成队列以供处理器子系统处理或从通用适配器输入传送 /输出端口。通用适配器管理器准备对作为通信服务的当前请求的功能的通信服务的预期请求的未来响应，诸如通过当前接收数据的请求准备对下一个缓冲区的预期请求的响应。通用适配器管理器将将来的响应存储在可由请求者读取的存储器中的指定地址处。每个通用适配器输入/输出端口具有与其相关联的分组存储器接口，用于将数据分组传入和传出分组存储器，使得当在输入/输出端口处接收到数据分组时，将数据分组转移到适配器包内存并排队处理。

17. 发明授权

US5367643A Generic high bandwidth adapter having data packet memory configured in three level hierarchy for temporary storage of variable length data packets 失效
标题翻译：通用高带宽适配器具有配置在三级层级中的数据分组存储器，用于临时存储可变长度数据分组
公开(公告)号：US5367643A
公开(公告)日：1994-11-22
申请号：US651894
申请日：1991-02-06
申请人： Paul Chang , Gary S. Delp , Hanafy E. Meleis , Rafael M. Montalvo , David I. Seidman , Ahmed N. Tantawy , Dominick A. Zumbo
发明人： Paul Chang , Gary S. Delp , Hanafy E. Meleis , Rafael M. Montalvo , David I. Seidman , Ahmed N. Tantawy , Dominick A. Zumbo
IPC分类号： G06F13/00 , G06F5/06 , G06F13/12 , G06F13/38 , H04L12/18 , H04L12/56 , H04L29/10
CPC分类号： H04L49/9026 , G06F13/128 , G06F13/387 , G06F5/06 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9047 , H04L12/18 , H04L49/205 , H04L49/3027 , H04L49/351
摘要： A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.
摘要翻译：通用高带宽适配器，为总线，通道，处理器，交换结构和/或通信网络之间的数据通信提供统一架构。数据由可变长度的数据流分组携带，每个分组包括用于调停信息交换的通信协议所需的报头控制信息部分，通常是要传送的数据的数据部分。通用高带宽适配器包括处理器子系统，其包括用于处理数据分组的报头控制信息部分的处理器。处理器可以访问存储在分组存储器中的数据分组，其存储到达四个通用适配器输入/输出端口的数据分组。分组存储器被分割成多个缓冲器，并且每个数据分组根据其长度的要求存储在一个或多个缓冲器中。提供通用适配器管理器，用于执行和同步通用适配器管理功能，包括通过在缓冲器中组织数据分组来实现分组存储器中的数据结构，以及将数据分组组织成队列以供处理器子系统处理或从通用适配器输入传送 /输出端口。每个通用适配器输入/输出端口具有与其相关联的分组存储器接口，用于将数据分组传入和传出分组存储器，使得当在输入/输出端口处接收到数据分组时，将数据分组转移到适配器包内存并排队处理。

18. 发明授权

US5260942A Method and apparatus for batching the receipt of data packets 失效
标题翻译：批量接收数据包的方法和装置
公开(公告)号：US5260942A
公开(公告)日：1993-11-09
申请号：US847470
申请日：1992-03-06
申请人： Richard A. Auerbach , Jerry A. Blades , Jonathan W. Byrn , Gary S. Delp
发明人： Richard A. Auerbach , Jerry A. Blades , Jonathan W. Byrn , Gary S. Delp
IPC分类号： H04L12/56 , H04L29/06 , H04J3/14
CPC分类号： H04L12/56 , H04L29/06 , H04L69/22
摘要： A method and a system in a distributed data processing network for enhancing the processing of a plurality of related data packets received at a receiving station within the distributed data processing network, each of the data packets having a header associated herewith includes sequentially receiving a number of data packets at the receiving station. Next, the header associated with a first data packet is examined and predicted profile is generated for comparison with a related subsequent data packet. The next data packet received is then compared with the predicted profile to determine whether or not the two data packets may be consolidated.

19. 发明授权

US07620924B2 Base platforms with combined ASIC and FPGA features and process of using the same 有权
标题翻译：具有ASIC和FPGA组合的基本平台功能及其使用过程
公开(公告)号：US07620924B2
公开(公告)日：2009-11-17
申请号：US11079439
申请日：2005-03-14
申请人： Gary S. Delp , George Wayne Nation
发明人： Gary S. Delp , George Wayne Nation
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.
摘要翻译：公开了一种用于配置具有ASIC和FPGA模块以执行多个功能的基础平台的过程。对电路的验证RTL硬件描述进行映射和注释，以识别存储器可编程功能。存储器可编程功能被分组以分配给FPGA模块。非存储器可编程功能被合成到ASIC模块，并且存储器可编程功能被合成到FPGA模块。完成放置，信号路由和边界定时关闭，并通过添加金属化层来配置ASIC模块并创建固件存储器来配置FPGA模块来配置平台。 FPGA模块中的过度供应功能允许逻辑功能的后制造改变。

20. 发明授权

US07496861B2 Method for generalizing design attributes in a design capture environment 失效
标题翻译：在设计捕获环境中概括设计属性的方法
公开(公告)号：US07496861B2
公开(公告)日：2009-02-24
申请号：US11290186
申请日：2005-11-30
申请人： George W. Nation , Gary Lippert , Gary S. Delp
发明人： George W. Nation , Gary Lippert , Gary S. Delp
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for generalizing design attributes in a design capture environment comprising the steps of (A) defining a procedure for adding one or more auxiliary configurators to a tool or suite of tools, (B) linking the auxiliary configurators to predetermined object points in an abstracted design and (C) defining a procedure for the tool or suite of tools to reference the one or more auxiliary configurators, wherein the auxiliary configurators are neither referenced by a core nor built into the tool or suite of tools.
摘要翻译：一种用于在设计捕获环境中概括设计属性的方法，包括以下步骤：（A）定义用于将一个或多个辅助配置器添加到工具或工具套件的过程，（B）将辅助配置器链接到抽象的预定对象点设计和（C）定义用于参考一个或多个辅助配置器的工具或工具套件的过程，其中辅助配置器既不被核心引用也不内置在工具或工具套件中。

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