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11. 发明申请

US20070061665A1 Clock and data recovery system and method for clock and data recovery based on a forward error correction 有权
标题翻译：基于前向纠错的时钟和数据恢复系统及时钟和数据恢复方法
公开(公告)号：US20070061665A1
公开(公告)日：2007-03-15
申请号：US11214161
申请日：2005-08-29
申请人： Hayden Cranford , Martin Schmatz , Thomas Toifl
发明人： Hayden Cranford , Martin Schmatz , Thomas Toifl
IPC分类号： H03M13/00
CPC分类号： H03M13/336 , H03L7/091 , H04L1/0053 , H04L1/0061 , H04L7/033 , H04L7/048
摘要： The forward error correction based clock and data recovery system according to the invention comprises a data latch (16) for intermediately storing received data, which is triggered by a sampling clock (sclk). The system further comprises an error determination unit (20, 21) for determining whether and which of the sampled received data is wrong, and for generating out of it a phase/frequency correction signal (ctrl). Furthermore, the system comprises a clock generator (23, 24, 25) for generating the sampling clock (sclk) depending on the correction signal (ctrl).
摘要翻译：根据本发明的基于前向纠错的时钟和数据恢复系统包括用于中间存储由采样时钟（sclk）触发的接收数据的数据锁存器（16）。该系统还包括用于确定采样的接收数据是否以及哪个是错误的并且用于产生相位/频率校正信号（ctrl）的错误确定单元（20,21）。此外，该系统包括用于根据校正信号（ctrl）产生采样时钟（sclk）的时钟发生器（23,24,25）。

12. 发明申请

US20060209944A1 Altering power consumption in communication links based on measured noise 有权
公开(公告)号：US20060209944A1
公开(公告)日：2006-09-21
申请号：US11079952
申请日：2005-03-15
申请人： Juan Carballo , Hayden Cranford , Gareth Nicholls , Vernon Norman , Brian Schuh
发明人： Juan Carballo , Hayden Cranford , Gareth Nicholls , Vernon Norman , Brian Schuh
IPC分类号： H04B17/00 , H03D1/04
CPC分类号： H04B17/382 , H04B17/24 , H04B17/345
摘要： A method, circuit and system for altering the power consumption in communication links. A type of noise and an amount of jitter in a signal transmitted across a communication link is measured. Upon determining the contribution of the measured noise to the measured jitter in the signal, the measured noise is classified based on such contribution and the intensity of the measured jitter. The power consumption in a component(s) of the communication link may be adjusted based on the classification of the measured noise. For example, if the measured noise is classified as being a low amount of noise, then the power consumption of the component(s) may be reduced such as by lowering the voltage of the power supply and/or reducing the complexity of the circuitry. By reducing the power consumption when the communication link is not subject to the worst-case condition, a savings in power consumption may be made.

13. 发明申请

US20050195863A1 Circuit and method for providing automatic adaptation to frequency offsets in high speed serial links 有权
标题翻译：用于在高速串行链路中提供自动适应频率偏移的电路和方法
公开(公告)号：US20050195863A1
公开(公告)日：2005-09-08
申请号：US10791175
申请日：2004-03-02
申请人： Hayden Cranford , Gareth Nicholls , Bobak Modaress-Razavi , Vernon Norman , Martin Schmatz
发明人： Hayden Cranford , Gareth Nicholls , Bobak Modaress-Razavi , Vernon Norman , Martin Schmatz
IPC分类号： H03L7/07 , H03L7/081 , H03L7/093 , H04L27/00 , H04J3/06
CPC分类号： H03L7/0814 , H03L7/07 , H04L2027/0065 , H04L2027/0067
摘要： Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.
摘要翻译：描述了在高速串行链路中提供对频偏的自动适配的方面。通过检测第一信号中的趋势来产生第二信号来调整在接收机链路中进行相位调整的第一信号，第二信号通过相位调整来提高对频偏的补偿率。包括一个向上/向下计数器，用于通过串行接收器的时钟数据恢复环来对信号进行相位调整。加法器耦合到上/下计数器并输出指示相位调整趋势的累加数据。耦合到加法器的组合逻辑基于累积数据来适配信号。

14. 发明申请

US20050111536A1 Method for determining jitter of a signal in a serial link and high speed serial link 有权
标题翻译：用于确定串行链路和高速串行链路中的信号抖动的方法
公开(公告)号：US20050111536A1
公开(公告)日：2005-05-26
申请号：US10720974
申请日：2003-11-24
申请人： Hayden Cranford , Marcel Kossel , Vernon Norman , Martin Schmatz
发明人： Hayden Cranford , Marcel Kossel , Vernon Norman , Martin Schmatz
IPC分类号： H04B3/46 , H04L1/20 , H04L25/06
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： The method for determining jitter of a signal in a serial link according to the invention comprising the following steps: First, a section of the signal transmitted via a transmission channel is sampled at different sampling times. The total number of edges in the section is determined. The neighboring sample values are analyzed and from that a statistical value is formed. From the statistical value and the total number of edges a figure of merit is determined. Finally, by means of a look-up table or a jitter-versus-figure of merit curve, the total jitter corresponding to the figure of merit is derived.
摘要翻译：根据本发明的用于确定串行链路中的信号的抖动的方法包括以下步骤：首先，经由传输信道发送的信号的一部分在不同的采样时间被采样。确定该部分中的边缘总数。分析相邻的样本值，并从中形成统计值。从统计值和总边缘数确定品质因数。最后，通过查询表或优点曲线的抖动对数值，推导出与品质因数对应的总抖动。

15. 发明申请

US20070242741A1 One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery 失效
标题翻译：单采样每位决策反馈均衡器（DFE）时钟和数据恢复
公开(公告)号：US20070242741A1
公开(公告)日：2007-10-18
申请号：US11405997
申请日：2006-04-18
申请人： Juan Carballo , Hayden Cranford , Gareth Nicholls , Vernon Norman , Martin Schmatz
发明人： Juan Carballo , Hayden Cranford , Gareth Nicholls , Vernon Norman , Martin Schmatz
IPC分类号： H03H7/30
CPC分类号： H04L25/03063
摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.
摘要翻译：公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。输入电压被转换为电流并连接到电流求和节点。由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。另外，总和电流被积分并转换成电压。采样器用于基于所得到的电压进行位决定。采样后，积分器在分析下一位之前被复位。通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。

16. 发明申请

US20070103173A1 Systems and Methods for Controlling of Electro-Migration 有权
标题翻译：控制电迁移的系统和方法
公开(公告)号：US20070103173A1
公开(公告)日：2007-05-10
申请号：US11566796
申请日：2006-12-05
申请人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
发明人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
IPC分类号： G01R27/08
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.
摘要翻译：公开了用于控制电迁移的系统和方法，并减少其有害影响。实施例提供了当指示电迁移程度的测量指示操作的愈合周期是有必要的时将施加的电压反转到集成电路。在愈合周期中，集成电路的电路正常工作，但电迁移效应相反。在一个实施例中，微电子机械开关设置在最低级别的金属化处，以将电流方向切换到集成电路的金属化水平。在另一个实施例中，如果指示电迁移程度的测量超过参考电平达指定量，则施加到集成电路的电压的极性反转，导致电流切换方向以对抗电迁移。提供多个开关以切换电流方向通过最低金属化水平，使得即使施加的电压的极性已经被反转，电路也能正常工作。

17. 发明申请

US20070069793A1 Method and system for high frequency clock signal gating 失效
标题翻译：高频时钟信号门控方法及系统
公开(公告)号：US20070069793A1
公开(公告)日：2007-03-29
申请号：US11235758
申请日：2005-09-27
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Samuel Ray , Wayne Utter
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Samuel Ray , Wayne Utter
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.
摘要翻译：提供了一种差分时钟信号门控方法和系统，其中时钟缓冲器电路控制路径产生与时钟信号的定时关系的时钟门控信号。时钟门控信号将响应于第一时钟信号脉冲负半部分的与时钟信号通信的时钟缓冲器电路控制路径上的缓冲器门控。缓冲器提供在第一时钟信号脉冲之后立即和顺序发生的第二和连续时钟信号脉冲，作为输出到第二级时钟路径中的第二缓冲级的缓冲时钟信号，每个具有标称时钟幅度和标称时钟脉冲宽度时钟信号无抖动。

18. 发明申请

US20060245507A1 High speed serial link output stage having self adaptation for various impairments 失效
标题翻译：具有各种损伤的自适应的高速串行链路输出级
公开(公告)号：US20060245507A1
公开(公告)日：2006-11-02
申请号：US11119505
申请日：2005-04-29
申请人： Steven Clements , Carrie Cox , Hayden Cranford
发明人： Steven Clements , Carrie Cox , Hayden Cranford
IPC分类号： H04L25/00
CPC分类号： H04L25/0292 , H04L25/03885
摘要： A high speed serial link structure and method are provided, comprising a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.
摘要翻译：提供了一种高速串行链路结构和方法，包括数据驱动器和复制驱动器结构，复制驱动器结构包括复制驱动器，校准引擎和峰值电平检测器。校准引擎将峰值电平检测器输出与参考值进行比较，并响应于执行数据驱动器调整，其中数据驱动器调整包括驱动器偏置调整，驱动器中间级带宽调整和驱动器均衡设置调整中的至少一个。在一些实施例中，校准引擎包括比较器和数字状态机; 在其他实施例中，它包括模拟运算放大器。

19. 发明申请

US20060029177A1 Unified digital architecture 失效
公开(公告)号：US20060029177A1
公开(公告)日：2006-02-09
申请号：US11249851
申请日：2005-10-13
申请人： Hayden Cranford , Vernon Norman , Martin Schmatz
发明人： Hayden Cranford , Vernon Norman , Martin Schmatz
IPC分类号： H03D3/24
CPC分类号： H03L7/08 , H03L7/095 , H03L7/0995 , H03L7/10 , H04L7/0337 , H04L2027/0067
摘要： A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.

20. 发明申请

US20050281355A1 Reducing power consumption in signal detection 有权
标题翻译：降低信号检测中的功耗
公开(公告)号：US20050281355A1
公开(公告)日：2005-12-22
申请号：US10873672
申请日：2004-06-22
申请人： Hayden Cranford , Westerfield Ficken
发明人： Hayden Cranford , Westerfield Ficken
IPC分类号： H04L27/06 , H04L27/08
CPC分类号： H04L27/06 , H04L27/08
摘要： Methods, systems, and media to time-share the signal detection between reference voltages for a data transmission are contemplated. Embodiments include a time-sharing detector that is designed to enable comparison of a first reference voltage and a second reference voltage against the serial data transmission in a specified pattern. In many embodiments, the pattern is pre-defined and, in some embodiments, the pattern includes an overlap period. During the overlap period both the first and the second reference voltages are compared with the data transmission to determine if valid data can be detected. Upon detecting a valid bit based upon one of the reference voltages, an output signal is generated to indicate that the data transmission includes a valid data signal. Advantageously, alternating between the comparisons can reduce power consumption. In many embodiments, the power reduction can be, for example, 50%, depending upon the specified pattern.
摘要翻译：考虑用于数据传输的参考电压之间的时间共享信号检测的方法，系统和媒体。实施例包括分时检测器，其被设计为能够以指定的模式与第一参考电压和第二参考电压相对于串行数据传输进行比较。在许多实施例中，图案是预定义的，并且在一些实施例中，图案包括重叠周期。在重叠期间，将第一和第二参考电压与数据传输进行比较，以确定是否可以检测有效数据。在基于参考电压之一检测到有效位时，产生输出信号以指示数据传输包括有效数据信号。有利地，比较之间的交替可以降低功耗。在许多实施例中，取决于指定的模式，功率降低可以是例如50％。

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