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11. 发明授权

US06717785B2 Semiconductor switching element driving circuit 有权
标题翻译：半导体开关元件驱动电路
公开(公告)号：US06717785B2
公开(公告)日：2004-04-06
申请号：US09819715
申请日：2001-03-29
申请人： Yutaka Fukuda , Ryoichi Okuda , Tomoatsu Makino , Kenji Yagi , Yukio Tsuzuki
发明人： Yutaka Fukuda , Ryoichi Okuda , Tomoatsu Makino , Kenji Yagi , Yukio Tsuzuki
IPC分类号： H02H308
CPC分类号： H03K17/0828 , H03K17/168
摘要： A semiconductor switching element driving circuit comprises an overcurrent limiting circuit which instantaneously drops a voltage of a gate terminal of an IGBT when a main IGBT current becomes larger than a predetermined level i1. An overcurrent protection circuit which first decreases the main IGBT current at a first inclination when the main IGBT current becomes larger than the other level i2 lower than the i1 and then reduces the main IGBT current at a steep second inclination when it becomes smaller than another level i3.
摘要翻译：半导体开关元件驱动电路包括当主IGBT电流变得大于预定电平i1时瞬时降低IGBT的栅极端子的电压的过电流限制电路。一个过电流保护电路，当主IGBT电流变得大于比i1低的另一个电平i2时，首先降低主IGBT电流，然后当其变得小于另一个电平时，以较陡峭的第二倾斜度降低主IGBT电流 i3。

12. 发明授权

US5138422A Semiconductor device which includes multiple isolated semiconductor segments on one chip 失效
标题翻译：在一个芯片上包括多个隔离半导体段的半导体器件
公开(公告)号：US5138422A
公开(公告)日：1992-08-11
申请号：US790025
申请日：1991-11-06
申请人： Tetsuo Fujii , Susumu Kuroyanagi , Yukio Tsuzuki
发明人： Tetsuo Fujii , Susumu Kuroyanagi , Yukio Tsuzuki
IPC分类号： H01L21/762 , H01L21/763 , H01L27/088
CPC分类号： H01L21/762 , H01L21/76248 , H01L21/76264 , H01L21/763 , H01L21/76272 , H01L21/76275 , H01L21/76286 , H01L27/088
摘要： Disclosed is a semiconductor device which comprises a substrate, an insulating film formed at a predetermined region in the substrate or on the main surface of the substrate, a polycrystalline semiconductor layer formed on at least the insulating film, a single crystal semiconductor layer formed on at least the polycrystalline semiconductor layer, an isolation region formed to extend from the top main surface of the single crystal semiconductor layer to at least the surface of the insulating film, through the polycrystalline semiconductor layer, to electrically isolate a portion formed in the single crystal semiconductor layer surrounded by the isolation region from another portion formed in the single crystal semiconductor layer and not surrounded by the isolation region, at least a semiconductor device formed within the portion surrounded by the isolation region. This semiconductor device has an additional characteristic in that another semiconductor device using another main surface of the substrate as the electrode is provided on the surface of the substrate and the single crystal semiconductor layer, and the plolycrystalline semiconductor layer serves to terminate the electric line of force emitted from the substrate, and therefore, the single crystal semiconductor layer mounted on the polycrystalline semiconductor layer is not affected by the electric line of force. Consequently, a semiconductor device which can operate effectively without being influenced by variations of the electric potential in the substrate can be obtained, and further, an intelligent type power device can be formed in which the power semiconductor device and the semiconductor device controlling the power device are formed in the same substrate but are completely isolated from each other.
摘要翻译：公开了一种半导体器件，其包括基板，形成在基板中或基板的主表面上的预定区域处的绝缘膜，形成在至少绝缘膜上的多晶半导体层，形成在基板上的单晶半导体层至少多晶半导体层，通过多晶半导体层形成为从单晶半导体层的顶部主表面延伸到至少绝缘膜的表面的隔离区，以将形成在单晶半导体中的部分电隔离所述隔离区域与形成在所述单晶半导体层中的不被所述隔离区域包围的另一部分包围的至少一个半导体器件形成在由所述隔离区域包围的部分内。该半导体器件具有另外的特征，即在衬底和单晶半导体层的表面上设置另一个使用衬底的另一个主表面作为电极的半导体器件，并且该结晶半导体层用于终止电力线从衬底发出的，因此，安装在多晶半导体层上的单晶半导体层不受电力线的影响。因此，可以获得能够有效地工作而不受基板中电位变化的影响的半导体器件，并且还可以形成智能型功率器件，其中功率半导体器件和控制功率器件的半导体器件形成在相同的基板中，但彼此完全隔离。

13. 发明授权

US5136348A Structure and manufacturing method for thin-film semiconductor diode device 失效
标题翻译：薄膜半导体二极管器件的结构和制造方法
公开(公告)号：US5136348A
公开(公告)日：1992-08-04
申请号：US647194
申请日：1991-01-28
申请人： Yukio Tsuzuki , Masami Yamaoka , Hiroshi Muto
发明人： Yukio Tsuzuki , Masami Yamaoka , Hiroshi Muto
IPC分类号： H01L27/06 , H01L27/12 , H01L29/04 , H01L29/78 , H01L29/861
CPC分类号： H01L29/7804 , H01L27/0688 , H01L27/12 , H01L29/04 , H01L29/861 , Y10S257/926
摘要： A structure and manufacturing method for a thin film semiconductor device consisting of a single diode or a plurality of diodes connected in series, the device being formed of at least one pair of mutually adjacent P-type (23a) and N-type (23b) regions formed in a layer of polycrystalline silicon (23) deposited on an insulating film (22) upon a substrate (21), to thereby define at least one PN junction. Each of the p-type regions and N-type regions is shaped as a rectangle, with opposite ends of each PN junction formed between these regions being respectively defined by two opposing sides of the polycrystalline silicon layer. Since each of the PN junctions is substantially rectilinear, an even distribution of current flow through each PN junction is attained, whereby a high resistance to destruction and an extremely stable value of reverse bias breakdown voltage are achieved.
摘要翻译：一种由串联连接的单个二极管或多个二极管组成的薄膜半导体器件的结构和制造方法，该器件由至少一对相互相邻的P型（23a）和N型（23b）形成，在衬底（21）上沉积在绝缘膜（22）上的多晶硅层（23）中形成的区域，从而限定至少一个PN结。每个p型区域和N型区域被成形为矩形，其中形成在这些区域之间的每个PN结的相对端分别由多晶硅层的两个相对侧限定。由于每个PN结基本上都是直线的，所以能够获得通过每个PN结的电流的平均分布，从而实现了高的抗破坏性和非常稳定的反向偏压击穿电压值。

14. 发明申请

US20130087829A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130087829A1
公开(公告)日：2013-04-11
申请号：US13805740
申请日：2011-06-29
申请人： Hiromitsu Tanabe , Kenji Kouno , Yukio Tsuzuki
发明人： Hiromitsu Tanabe , Kenji Kouno , Yukio Tsuzuki
IPC分类号： H01L27/07
CPC分类号： H01L27/0664 , H01L27/0722 , H01L29/0696 , H01L29/4236 , H01L29/66348 , H01L29/7395 , H01L29/7397 , H01L29/861
摘要： In a semiconductor device including an IGBT and a freewheeling diode (FWD), W1, W2, and W3 satisfy predetermined formulas. W1 denotes a distance from a boundary between a cathode region and a collector region to a position, where a peripheral-region-side end of the well layer is projected, on a back side of the drift layer. W2 denotes a distance from a boundary between the IGBT and the FWD in a base region to the peripheral-region-side end of the well layer. W3 denotes a distance from the boundary between the cathode region and the collector region to a position, where a boundary between the base region and the well layer is projected, on the back side.
摘要翻译：在包括IGBT和续流二极管（FWD）的半导体器件中，W1，W2和W3满足预定的公式。 W1表示从阴极区域和集电极区域之间的边界到阱层的周边区域侧端部投射在位于漂移层的背面的位置的距离。 W2表示从基极区域到阱区域的周边区域侧的IGBT与FWD之间的边界的距离。 W3表示从阴极区域和集电极区域之间的边界到背面侧的基底区域和阱层之间的边界的位置的距离。

15. 发明授权

US08405122B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US08405122B2
公开(公告)日：2013-03-26
申请号：US13010307
申请日：2011-01-20
申请人： Kenji Kouno , Yukio Tsuzuki
发明人： Kenji Kouno , Yukio Tsuzuki
IPC分类号： H01L29/66
CPC分类号： H01L29/7397 , H01L29/0619 , H01L29/0696 , H01L29/7391 , H01L29/7393 , H01L29/7394
摘要： An insulated gate semiconductor device includes a semiconductor substrate, channel regions, floating regions, an emitter region, a body region, a hole stopper layer, and an emitter electrode. The channel regions and the floating regions are repeatedly arranged such that at least one floating region is located between adjacent channel regions. The emitter region and the body region are located in a surface portion of each channel region. The body region is deeper than the emitter region. The hole stopper layer is located in each floating region to divide the floating region into a first region and a second region. The emitter electrode is electrically connected to the emitter region and the first region.
摘要翻译：绝缘栅半导体器件包括半导体衬底，沟道区，浮置区，发射区，体区，空穴阻挡层和发射极。沟道区域和浮置区域被重复布置，使得至少一个浮动区域位于相邻沟道区域之间。发射极区域和体区域位于每个沟道区域的表面部分中。身体区域比发射极区域更深。空穴阻挡层位于每个浮动区域中，以将浮动区域划分成第一区域和第二区域。发射极电极与发射极区域和第一区域电连接。

16. 发明申请

US20120132954A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120132954A1
公开(公告)日：2012-05-31
申请号：US13301973
申请日：2011-11-22
申请人： Kenji KOUNO , Hiromitsu Tanabe , Yukio Tsuzuki
发明人： Kenji KOUNO , Hiromitsu Tanabe , Yukio Tsuzuki
IPC分类号： H01L27/06 , H01L29/772 , H01L29/06
CPC分类号： H01L29/7397 , H01L29/0619 , H01L29/0696 , H01L29/0834 , H01L29/7811 , H01L29/7813 , H01L29/8611
摘要： A semiconductor device includes a semiconductor substrate with a first surface and a second surface. The semiconductor substrate has an element region including an IGBT region and a diode region located adjacent to the IGBT region. An IGBT element is formed in the IGBT region. A diode element is formed in the diode region. A heavily doped region of first conductivity type is located on the first surface side around the element region. An absorption region of first conductivity type is located on the second surface side around the element region. A third semiconductor region of second conductivity type is located on the second surface side around the element region.
摘要翻译：半导体器件包括具有第一表面和第二表面的半导体衬底。半导体基板具有包括IGBT区域和位于IGBT区域附近的二极管区域的元件区域。在IGBT区域中形成IGBT元件。在二极管区域中形成二极管元件。第一导电类型的重掺杂区域位于围绕元件区域的第一表面侧上。第一导电类型的吸收区域位于元件区域周围的第二表面侧。第二导电类型的第三半导体区域位于元件区域周围的第二表面侧。

17. 发明授权

US08168999B2 Semiconductor device having IGBT and diode 有权
标题翻译：具有IGBT和二极管的半导体器件
公开(公告)号：US08168999B2
公开(公告)日：2012-05-01
申请号：US12385164
申请日：2009-03-31
申请人： Yukio Tsuzuki , Kenji Kouno
发明人： Yukio Tsuzuki , Kenji Kouno
IPC分类号： H01L27/06 , H01L29/739
CPC分类号： H01L29/861 , H01L29/0619 , H01L29/167 , H01L29/407 , H01L29/7397 , H01L29/8611
摘要： A semiconductor device includes: a substrate; an active element cell area including IGBT cell region and a diode cell region; a first semiconductor region on a first side of the substrate in the active element cell area; a second semiconductor region on a second side of the substrate in the IGBT cell region; a third semiconductor region on the second side in the diode cell region; a fourth semiconductor region on the first side surrounding the active element cell area; a fifth semiconductor region on the first side surrounding the fourth semiconductor region; and a sixth semiconductor region on the second side below the fourth semiconductor region. The second semiconductor region, the third semiconductor region and the sixth semiconductor region are electrically coupled with each other.
摘要翻译：半导体器件包括：衬底; 包括IGBT单元区域和二极管单元区域的有源元件单元区域; 在所述有源元件单元区域中的所述基板的第一侧上的第一半导体区域; 在所述IGBT单元区域中的所述衬底的第二侧上的第二半导体区域; 在二极管单元区域中的第二侧上的第三半导体区域; 围绕所述有源元件单元区域的所述第一侧上的第四半导体区域; 围绕第四半导体区域的第一侧的第五半导体区域; 以及在第四半导体区域下方的第二侧上的第六半导体区域。第二半导体区域，第三半导体区域和第六半导体区域彼此电耦合。

18. 发明申请

US20100187567A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20100187567A1
公开(公告)日：2010-07-29
申请号：US12656340
申请日：2010-01-26
申请人： Hiromitsu Tanabe , Kenji Kouno , Yukio Tsuzuki , Shinji Amano
发明人： Hiromitsu Tanabe , Kenji Kouno , Yukio Tsuzuki , Shinji Amano
IPC分类号： H01L29/739
CPC分类号： H01L29/0834 , H01L29/0615 , H01L29/1095 , H01L29/7397 , H01L29/861 , H01L2924/0002 , H03K2217/0027 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate having a first surface and a second surface. A main region and a sensing region are formed on the first surface side of the semiconductor substrate. A RC-IGBT is formed in the main region and a sensing element for passing electric currents proportional to electric currents flowing through the RC-IGBT is formed in the sensing region. A collector region and a cathode region of the sensing element are formed on the second surface side of the semiconductor substrate. The collector region is located directly below the sensing region in a thickness direction of the semiconductor substrate. The cathode region is not located directly below the sensing region in the thickness direction.
摘要翻译：半导体器件包括具有第一表面和第二表面的半导体衬底。主区域和感测区域形成在半导体衬底的第一表面侧上。在主区域中形成RC-IGBT，并且在感测区域中形成用于使电流与流过RC-IGBT的电流成比例的电流的感测元件。感测元件的集电极区域和阴极区域形成在半导体衬底的第二表面侧上。集电极区域位于半导体基板的厚度方向的感测区域正下方。阴极区域不位于厚度方向的感测区域正下方。

19. 发明申请

US20090114947A1 Semiconductor device and inverter circiut having the same 有权
标题翻译：半导体装置和逆变器具有相同的回路
公开(公告)号：US20090114947A1
公开(公告)日：2009-05-07
申请号：US12289852
申请日：2008-11-06
申请人： Yutaka Fukuda , Yukio Tsuzuki
发明人： Yutaka Fukuda , Yukio Tsuzuki
IPC分类号： H01L27/06 , G05F1/10
CPC分类号： H01L29/7397 , H01L27/0664 , H01L27/0694 , H01L2924/0002 , H03K2217/0027 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, an insulated gate transistor formed to the semiconductor substrate, a diode formed to the semiconductor substrate, and a control transistor formed to the semiconductor substrate. A first current terminal of the insulated gate transistor is coupled to a cathode of the diode at a high potential side. A second current terminal of the insulated gate transistor is coupled to an anode of the diode at a low potential side. The control transistor is configured to turn off the insulated gate transistor by reducing a potential of a gate terminal of the insulated gate transistor when the diode conducts an electric current.
摘要翻译：半导体器件包括半导体衬底，形成于半导体衬底的绝缘栅晶体管，形成于半导体衬底的二极管，和形成于半导体衬底的控制晶体管。绝缘栅极晶体管的第一电流端子在高电位侧耦合到二极管的阴极。绝缘栅晶体管的第二电流端子在低电位侧耦合到二极管的阳极。控制晶体管被配置为当二极管导通电流时，通过减小绝缘栅极晶体管的栅极端子的电位来关断绝缘栅极晶体管。

20. 发明申请

US20090072339A1 Semiconductor device having diode and IGBT 有权
标题翻译：具有二极管和IGBT的半导体器件
公开(公告)号：US20090072339A1
公开(公告)日：2009-03-19
申请号：US12222557
申请日：2008-08-12
申请人： Yukio Tsuzuki , Kenji Kouno
发明人： Yukio Tsuzuki , Kenji Kouno
IPC分类号： H01L29/06
CPC分类号： H01L27/0676 , H01L29/0623 , H01L29/7395 , H01L29/872
摘要： A semiconductor device includes: a semiconductor substrate including a first conductive type layer; a plurality of IGBT regions, each of which provides an IGBT element; and a plurality of diode regions, each of which provides a diode element. The plurality of IGBT regions and the plurality of diode regions are alternately arranged in the substrate. Each diode region includes a Schottky contact region having a second conductive type. The Schottky contact region is configured to retrieve a minority carrier from the first conductive type layer. The Schottky contact region is disposed in a first surface portion of the first conductive type layer, and adjacent to the IGBT region.
摘要翻译：半导体器件包括：包括第一导电类型层的半导体衬底; 多个IGBT区域，每个IGBT区域提供IGBT元件; 以及多个二极管区域，每个二极管区域提供二极管元件。多个IGBT区域和多个二极管区域交替地布置在基板中。每个二极管区域包括具有第二导电类型的肖特基接触区域。肖特基接触区域被配置为从第一导电类型层检索少数载流子。肖特基接触区域设置在第一导电类型层的第一表面部分中，并且与IGBT区域相邻。

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