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11. 发明授权

US4752913A Random access memory employing complementary transistor switch (CTS) memory cells 失效
标题翻译：采用互补晶体管开关（CTS）存储单元的随机存取存储器
公开(公告)号：US4752913A
公开(公告)日：1988-06-21
申请号：US857903
申请日：1986-04-30
申请人： Yuen H. Chan , James R. Struk
发明人： Yuen H. Chan , James R. Struk
IPC分类号： G11C11/413 , G11C11/411 , G11C11/415 , G11C11/416 , G11C11/417 , G11C7/00
CPC分类号： G11C11/416 , G11C11/4113 , G11C11/417
摘要： Disclosed is an improved bit selection circuit for a RAM, in particular one employing CTS (complementary transistor switch) cells. The bit select circuitry includes interconnected first and second level matrix decoders, each memory column has a pair of bit lines, each pair of bit lines has connected thereto a bit select circuit, each of the bit select circuits being connected to an output of the second level decoder, a bit up-level clamp circuit connected to each of the bit select circuits of each pair of bit lines, each of the bit select circuits including a first circuit for increasing the speed of selection of the selected pair of lines, the bit up-level clamp circuit cooperating with the bit select circuit of the selected pair of bit lines for positively limiting the upper potential level of the selected pair of bit lines, and each of the bit select circuits including a second circuit for increasing the speed of deselection of the selected pair of bit lines.
摘要翻译：公开了一种用于RAM的改进位选择电路，特别是采用CTS（互补晶体管开关）单元的位选择电路。位选择电路包括互连的第一和第二级矩阵解码器，每个存储器列具有一对位线，每对位线连接到位选择电路，每个位选择电路连接到第二级电平解码器，连接到每对位线的每个位选择电路的位上电平钳位电路，每个位选择电路包括用于增加所选择的一对线的选择速度的第一电路，位上位钳位电路与所选择的位线对的位选择电路协作，用于积极地限制所选择的位线对的上电位电平，并且每个位选择电路包括用于增加取消选择速度的第二电路的所选位线对。

12. 发明授权

US4529894A Means for enhancing logic circuit performance 失效
标题翻译：提高逻辑电路性能的手段
公开(公告)号：US4529894A
公开(公告)日：1985-07-16
申请号：US273706
申请日：1981-06-15
申请人： Yuen H. Chan , James E. Dickerson , Walter S. Klara , Theodore W. Kwap , Joseph M. Mosley
发明人： Yuen H. Chan , James E. Dickerson , Walter S. Klara , Theodore W. Kwap , Joseph M. Mosley
IPC分类号： H03K5/12 , H03K17/04 , H03K19/013 , H03K19/086 , H03K19/01 , H03K19/082
CPC分类号： H03K19/0136
摘要： Disclosed is a means for enhancing logic circuit performance and more particularly, for enhancing the switching speeds of a variety of logic circuits. What is involved is the insertion of a so called "snap" or enhancement transistor connected to a common node defining an output of a basic logic circuit. In one example, the emitter of this "snap" transistor is connected to an output node in the circuit, which in conventional practice would be charged during an upgoing transition by a fixed RC time constant. In accordance with the present improvement, however, the "snap" transistor, due to charge stored therein, remains conducting--although the associated logic device is turned off. This current discharges as reverse base current and the output provides what appears to be an inductive voltage spike. The effect is that a temporary source of current is available to charge the common node. As a result, the transition time involved in going from one voltage level to another at the output node is substantially reduced.
摘要翻译：公开了用于增强逻辑电路性能的手段，更具体地说，用于增强各种逻辑电路的切换速度。所涉及的是将所谓的“卡扣”或增强型晶体管插入连接到限定基本逻辑电路的输出的公共节点。在一个示例中，该“捕捉”晶体管的发射极连接到电路中的输出节点，其在常规实践中将在上行转换期间被固定的RC时间常数充电。然而，根据本发明的改进，由于存储在其中的电荷，“卡扣”晶体管保持导通，尽管关联的逻辑器件被关断。该电流作为反向基极电流放电，并且输出提供看起来是感应电压尖峰。效果是临时的电流源可用于对公共节点充电。结果，显着减少了在输出节点从一个电压电平转到另一个电压电平的过渡时间。

13. 发明授权

US08299833B2 Programmable control clock circuit including scan mode 失效
标题翻译：可编程控制时钟电路包括扫描模式
公开(公告)号：US08299833B2
公开(公告)日：2012-10-30
申请号：US12796970
申请日：2010-06-09
申请人： Paul A. Bunce , Yuen H. Chan , John D. Davis , Richard E. Serton
发明人： Paul A. Bunce , Yuen H. Chan , John D. Davis , Richard E. Serton
IPC分类号： H03K3/017
CPC分类号： H03K5/156
摘要： A programmable clock control circuit includes a base block configured to control operation of the programmable clock control circuit and a chop block configured to control the width of an output clock signal of the programmable clock control circuit. The circuit also includes a pulse width variation block providing a pulse width variation output to the base block, the base block output being variable to provide at least three different output pulse widths. The circuit also includes a launch clock delay block coupled to delay the output of the base block and a scan clock delay block to delay the output pulse and a selector that causes either the scan clock delay block or the launch clock delay block to be active based on a value of a scan gate signal.
摘要翻译：可编程时钟控制电路包括被配置为控制可编程时钟控制电路的操作的基本块和被配置为控制可编程时钟控制电路的输出时钟信号的宽度的斩波块。电路还包括提供脉冲宽度变化输出到基本块的脉冲宽度变化块，基本块输出是可变的以提供至少三个不同的输出脉冲宽度。电路还包括发射时钟延迟块，其耦合以延迟基本块的输出和延迟输出脉冲的扫描时钟延迟块和使得扫描时钟延迟块或启动时钟延迟块基于有源的选择器对扫描门信号的值。

14. 发明申请

US20110310680A1 Interleave Memory Array Arrangement 审中-公开
标题翻译：交错内存阵列布置
公开(公告)号：US20110310680A1
公开(公告)日：2011-12-22
申请号：US12821064
申请日：2010-06-22
申请人： Yuen H. Chan , Michael Kugel , Raphael Polig , Tobias Werner
发明人： Yuen H. Chan , Michael Kugel , Raphael Polig , Tobias Werner
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/08 , G11C7/1006 , G11C8/10
摘要： A memory array includes a plurality of memory cells, wherein each cell of the plurality of memory cells is defined by a row and a column, wherein each row includes a unique identifying address, and wherein each column is associated with one of two sets, the columns arranged such that a column associated with a first set is adjacent to a column of a second set.
摘要翻译：存储器阵列包括多个存储器单元，其中多个存储器单元中的每个单元由行和列定义，其中每行包括唯一的标识地址，并且其中每列与两组中的一个相关联，列排列成使得与第一组相关联的列与第二组的列相邻。

15. 发明申请

US20110298500A1 SINGLE CLOCK DYNAMIC COMPARE CIRCUIT 有权
标题翻译：单时钟动态比较电路
公开(公告)号：US20110298500A1
公开(公告)日：2011-12-08
申请号：US12792475
申请日：2010-06-02
申请人： Yuen H. Chan , Antonio R. Pelella , Richard E. Serton , Arthur Tuminaro
发明人： Yuen H. Chan , Antonio R. Pelella , Richard E. Serton , Arthur Tuminaro
IPC分类号： H03K5/00
CPC分类号： H03K19/20
摘要： A compare circuit for comparing a first data word with a second data word includes a plurality of sub-circuits, each having a two-bit static compare stage and a dynamic complex logic stage; a dynamic compare node responsive to respective outputs of the sub-circuits; and an output latch that captures a comparison result in accordance with a logic state of the dynamic compare node. In an exemplary embodiment, a local clock generator provides a single controlling clock signal for clocking the output latch, precharging of the dynamic compare node, and clocking of the dynamic complex logic stage of the sub-circuits.
摘要翻译：用于比较第一数据字与第二数据字的比较电路包括多个子电路，每个子电路具有两位静态比较级和动态复合逻辑级; 响应于子电路的相应输出的动态比较节点; 以及输出锁存器，其根据动态比较节点的逻辑状态捕获比较结果。在示例性实施例中，本地时钟发生器提供单个控制时钟信号，用于对输出锁存器进行计时，动态比较节点的预充电以及子电路的动态复合逻辑级的计时。

16. 发明申请

US20110075504A1 Dual Beta Ratio SRAM 有权
标题翻译：双倍比率SRAM
公开(公告)号：US20110075504A1
公开(公告)日：2011-03-31
申请号：US12566862
申请日：2009-09-25
申请人： Yuen H. Chan , Louis C. Hsu , Xu Ouyang , Robert C. Wong
发明人： Yuen H. Chan , Louis C. Hsu , Xu Ouyang , Robert C. Wong
IPC分类号： G11C8/16 , G11C11/00
CPC分类号： G11C8/16 , G11C11/412
摘要： A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes a plurality of SRAM cells, an SRAM cell including a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio.
摘要翻译：静态随机存取存储器（SRAM）单元包括第一读取端口，第一读取端口具有第一β比率; 和写入端口，所述写入端口具有基本上低于所述第一β比率的第二β比率。静态随机存取存储器（SRAM）阵列包括多个SRAM单元，包括第一读取端口的SRAM单元，第一读取端口具有第一β比率; 和写入端口，所述写入端口具有基本上低于所述第一β比率的第二β比率。

17. 发明授权

US07606060B2 Eight transistor SRAM cell with improved stability requiring only one word line 失效
标题翻译：八个晶体管SRAM单元具有改进的稳定性，只需要一个字线
公开(公告)号：US07606060B2
公开(公告)日：2009-10-20
申请号：US11832190
申请日：2007-08-01
申请人： Yuen H. Chan , William V. Huott , Donald W. Plass
发明人： Yuen H. Chan , William V. Huott , Donald W. Plass
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C8/14
摘要： An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.
摘要翻译：由单个字线访问的SRAM单元和用于读取和写入操作的单独的存取晶体管。一对写位线传输器件分别提供用于写操作的交叉耦合上拉，下拉晶体管对的右侧和左侧的访问以及与字线晶体管串联的单个读取位线晶体管，当选中，读取单元格的内容。

18. 发明申请

US20090189675A1 HIGH PERFORMANCE PSEUDO DYNAMIC PULSE CONTROLLABLE MULTIPLEXER 失效
标题翻译：高性能PSEUDO动态脉冲控制多路复用器
公开(公告)号：US20090189675A1
公开(公告)日：2009-07-30
申请号：US12021454
申请日：2008-01-29
申请人： Yuen H. Chan , Ann H. Chen , Antonio R. Pelella , Shie-ei Wang
发明人： Yuen H. Chan , Ann H. Chen , Antonio R. Pelella , Shie-ei Wang
IPC分类号： H03K17/284
CPC分类号： H03K17/693 , H03K17/005
摘要： A high performance, set associative, cache memory tag multiplexer provides wide output pulse width without impacting hold time by separating the evaluation and restore paths and using a wider clock in the restore path than in the evaluation path. A clock controls the evaluation of the input signals. Its leading edge (i.e., rising edge) turns on NR to allow evaluation, its trailing edge (falling edge) turns off NR to stop evaluation. At this point, when NR is shut off, the inputs can start changing to set up for the next cycle. Hence the hold time of the input is determined by the clock trailing edge.
摘要翻译：高性能，集合关联的高速缓存存储器标签多路复用器通过分离评估和恢复路径以及在还原路径中比在评估路径中使用更宽的时钟，提供宽的输出脉冲宽度而不影响保持时间。时钟控制输入信号的评估。其前沿（即上升沿）打开NR以允许评估，其后沿（下降沿）关闭NR以停止评估。此时，当NR关闭时，输入可以开始改变以设置下一个周期。因此，输入的保持时间由时钟后沿决定。

19. 发明申请

US20090063774A1 High Performance Pseudo Dynamic 36 Bit Compare 有权
标题翻译：高性能伪动态36位比较
公开(公告)号：US20090063774A1
公开(公告)日：2009-03-05
申请号：US11850050
申请日：2007-09-05
申请人： Yuen H. Chan , Ann H. Chen , Kenneth M. Lo , Shie-ei Wang
发明人： Yuen H. Chan , Ann H. Chen , Kenneth M. Lo , Shie-ei Wang
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/1045
摘要： A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static logic elements. The output of each of these static comparators is then combined in a dynamic logic circuit to generate a dynamic late select output.
摘要翻译：高速缓存高性能伪动态地址比较路径将地址分为两个或更多个地址段。在由静态逻辑元件组成的比较器中，每个段被单独比较。然后将这些静态比较器中的每一个的输出组合在动态逻辑电路中以产生动态后期选择输出。

20. 发明授权

US07483322B2 Ring oscillator row circuit for evaluating memory cell performance 失效
标题翻译：用于评估存储单元性能的环形振荡器行电路
公开(公告)号：US07483322B2
公开(公告)日：2009-01-27
申请号：US11963794
申请日：2007-12-22
申请人： Rajiv V. Joshi , Qiuyi Ye , Yuen H. Chan , Anirudh Devgan
发明人： Rajiv V. Joshi , Qiuyi Ye , Yuen H. Chan , Anirudh Devgan
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C29/50012
摘要： A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
摘要翻译：用于评估存储单元性能的环形振荡器行电路在实际的存储器电路环境中提供电路延迟和性能测量。环形振荡器用一行存储器单元实现，并且具有连接到一个或多个位线以及与环形振荡器单元基本相同的其它存储器单元的输出。可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

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