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    • 2. 发明授权
    • Means for enhancing logic circuit performance
    • 提高逻辑电路性能的手段
    • US4529894A
    • 1985-07-16
    • US273706
    • 1981-06-15
    • Yuen H. ChanJames E. DickersonWalter S. KlaraTheodore W. KwapJoseph M. Mosley
    • Yuen H. ChanJames E. DickersonWalter S. KlaraTheodore W. KwapJoseph M. Mosley
    • H03K5/12H03K17/04H03K19/013H03K19/086H03K19/01H03K19/082
    • H03K19/0136
    • Disclosed is a means for enhancing logic circuit performance and more particularly, for enhancing the switching speeds of a variety of logic circuits. What is involved is the insertion of a so called "snap" or enhancement transistor connected to a common node defining an output of a basic logic circuit. In one example, the emitter of this "snap" transistor is connected to an output node in the circuit, which in conventional practice would be charged during an upgoing transition by a fixed RC time constant. In accordance with the present improvement, however, the "snap" transistor, due to charge stored therein, remains conducting--although the associated logic device is turned off. This current discharges as reverse base current and the output provides what appears to be an inductive voltage spike. The effect is that a temporary source of current is available to charge the common node. As a result, the transition time involved in going from one voltage level to another at the output node is substantially reduced.
    • 公开了用于增强逻辑电路性能的手段,更具体地说,用于增强各种逻辑电路的切换速度。 所涉及的是将所谓的“卡扣”或增强型晶体管插入连接到限定基本逻辑电路的输出的公共节点。 在一个示例中,该“捕捉”晶体管的发射极连接到电路中的输出节点,其在常规实践中将在上行转换期间被固定的RC时间常数充电。 然而,根据本发明的改进,由于存储在其中的电荷,“卡扣”晶体管保持导通,尽管关联的逻辑器件被关断。 该电流作为反向基极电流放电,并且输出提供看起来是感应电压尖峰。 效果是临时的电流源可用于对公共节点充电。 结果,显着减少了在输出节点从一个电压电平转到另一个电压电平的过渡时间。