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11. 发明申请

US20070067612A1 Arithmetic operation apparatus, information processing apparatus, and register file control method 失效
标题翻译：算术运算装置，信息处理装置和寄存器文件控制方法
公开(公告)号：US20070067612A1
公开(公告)日：2007-03-22
申请号：US11333229
申请日：2006-01-18
申请人： Ryuji Kan , Hideo Yamashita , Toshio Yoshida
发明人： Ryuji Kan , Hideo Yamashita , Toshio Yoshida
IPC分类号： G06F9/44
CPC分类号： G06F9/30043 , G06F9/30127 , G06F9/3851
摘要： The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in the replacing buffer; and a control unit which transfers, if a window switching instruction is decoded at execution of the window switching instruction by the arithmetic operation unit, data of the register window which is to be specified by the current window pointer upon completion of execution of the window switching instruction, to the replacing buffer.
摘要翻译：本装置在采用无序指令执行方法的信息处理装置中减少硬件资源并提高数据读取吞吐量。该装置包括：算术运算单元，执行窗口切换指令和与存储在当前寄存器中的数据或保存在替换缓冲器中的数据有关的指令; 以及控制单元，如果在由算术运算单元执行窗口切换指令时对窗口切换指令进行了解码，则在完成窗口切换的执行完成后由当前窗口指针指定的寄存器窗口的数据指令，到替换缓冲区。

12. 发明申请

US20100095156A1 INFORMATION PROCESSING APPARATUS AND CONTROL METHOD 失效
标题翻译：信息处理装置和控制方法
公开(公告)号：US20100095156A1
公开(公告)日：2010-04-15
申请号：US12635896
申请日：2009-12-11
申请人： Ryuji KAN
发明人： Ryuji KAN
IPC分类号： G06F11/28
CPC分类号： G06F11/1064 , G06F9/30105 , G06F9/30127 , G06F9/30138 , G06F9/3865 , G06F11/2215 , G06F11/2236
摘要： A processing apparatus includes: first and second register files, the latter holding a part of data in the former; an operation unit to operate on data in the second register file and to output data; an instruction unit to issue a write instruction to write, to both register files, the output data and an error detection code for it, and first and second occurrence instructions; a first control unit to issue a first generation instruction when receiving the write instruction and the first occurrence instructions; and a first generation unit to generate a first simulated fault data to output it to the first register file when receiving the first generation instruction, and to output the output data and the error detection code to the first register file in absence of the first generation instruction. Similar second control and generation units are also provided mutatis mutandis.
摘要翻译：一种处理装置包括：第一和第二寄存器文件，后者保存前者中的一部分数据; 操作单元，用于对所述第二寄存器堆中的数据进行操作并输出数据; 发出写入指令的指令单元，向两个寄存器文件写入输出数据及其错误检测码，以及第一和第二次发生指令; 第一控制单元，当接收到写入指令和第一次发生指令时发出第一代指令; 以及第一生成单元，用于在接收到第一生成指令时生成第一模拟故障数据以将其输出到第一寄存器文件，并且在没有第一生成指令的情况下将输出数据和错误检测代码输出到第一寄存器堆。相应的第二控制和发电单位也经过必要的修改。

13. 发明申请

US20080307029A1 Arithmetic device and arithmetic method 审中-公开
标题翻译：算术装置和算术方法
公开(公告)号：US20080307029A1
公开(公告)日：2008-12-11
申请号：US12222521
申请日：2008-08-11
申请人： Ryuji Kan
发明人： Ryuji Kan
IPC分类号： G06F7/42 , G06F7/44
CPC分类号： G06F7/483 , G06F2207/3868
摘要： An FMA arithmetic unit has a timing control circuit. The timing control circuit controls bypass selectors to bypass intermediate resisters on performing floating point addition/subtraction, controls another bypass selector to bypass another intermediate register on performing floating point multiplication, and controls still another bypass selectors to bypass a register file/other arithmetic unit result register and operand registers on performing successive FMA arithmetic operations.
摘要翻译： FMA运算单元具有定时控制电路。定时控制电路控制旁路选择器在执行浮点加法/减法时旁路中间寄存器，控制另一个旁路选择器在执行浮点乘法时绕过另一个中间寄存器，并控制另一个旁路选择器绕过寄存器文件/其他算术单元结果寄存器和操作数寄存器执行连续的FMA算术运算。

14. 发明申请

US20080229080A1 ARITHMETIC PROCESSING UNIT 审中-公开
标题翻译：算术处理单元
公开(公告)号：US20080229080A1
公开(公告)日：2008-09-18
申请号：US12037395
申请日：2008-02-26
申请人： Ryuji KAN , Tomohiro TANAKA , Toshio YOSHIDA
发明人： Ryuji KAN , Tomohiro TANAKA , Toshio YOSHIDA
IPC分类号： G06F9/302
CPC分类号： G06F9/30043 , G06F9/30076 , G06F9/30098 , G06F9/30101 , G06F9/3012 , G06F9/30127 , G06F9/3824 , G06F9/3826 , G06F9/384 , G06F9/3842 , G06F9/3867 , G06F9/462
摘要： An arithmetic processing unit includes a register file provided with multiple register windows, an arithmetic executor executes an instruction with data retained in the register file as an operand, and a current window pointer which retains address information specifying a register window which becomes a current window, and a controller. The controller controls the address information retained by the current window pointer is updated, when a window switching instruction for indicating switching of the current window has been decoded. The arithmetic executor reads data in a first register window specified by the address information before being updated and data in a second register window specified by the updated address information from the register file, after the decoding of said window switching instruction has been started until commit of the window switching instruction is started.
摘要翻译：算术处理单元包括具有多个寄存器窗口的寄存器文件，算术执行器执行具有作为操作数保留在寄存器堆中的数据的指令，以及保持指定成为当前窗口的寄存器窗口的地址信息的当前窗口指针，和控制器。当用于指示当前窗口的切换的窗口切换指令已被解码时，控制器控制由当前窗口指针保留的地址信息被更新。算术执行器在所述窗口切换指令的解码已经开始直到所述窗口切换指令的解码之后，在被更新之前由地址信息指定的第一寄存器窗口中的数据和由所述更新的地址信息由所述寄存器文件指定的第二寄存器窗口中的数据进行读取窗口切换指令开始。

15. 发明授权

US08903881B2 Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit 有权
标题翻译：算术电路，运算处理装置及运算电路的控制方法
公开(公告)号：US08903881B2
公开(公告)日：2014-12-02
申请号：US13437969
申请日：2012-04-03
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42 , G06F7/483 , G06F7/499
CPC分类号： G06F7/49942 , G06F7/483
摘要： An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit.
摘要翻译：用于量化预量化数据的算术电路包括：第一输入寄存器，用于存储包括尾数和指数的第一格式的预量化数据;存储量化目标指数的第二输入寄存器;指数校正值指示单元指示指数校正值，指数生成单元，用于生成通过从量化目标指数中减去指数校正值而获得的量化指数;移位量生成单元，生成通过减去预量化数据的指数得到的移位量以及来自量化目标指数的指数校正值，用于生成通过将预量化数据的尾数偏移由移位量产生单元生成的移位量而获得的量化尾数的移位单元和用于存储量化数据的输出寄存器其包括由指数生成单元生成的量化指数和量化的尾数gen 由换档单元擦除。

16. 发明授权

US08788561B2 Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit 失效
标题翻译：算术电路，运算处理装置及运算电路的控制方法
公开(公告)号：US08788561B2
公开(公告)日：2014-07-22
申请号：US13441020
申请日：2012-04-06
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42
CPC分类号： G06F7/483 , G06F7/49942
摘要： An arithmetic circuit calculates a correction value for a value that is obtained by an add-subtract operation of two values and that is expressed in a predetermined fixed precision.
摘要翻译：算术电路计算通过两个值的加减运算获得的并以预定的固定精度表示的值的校正值。

17. 发明授权

US08655935B2 Processing apparatus and control method performing taylor series operation associated with executing floating point instruction 有权
标题翻译：执行与执行浮点指令相关的泰勒系列操作的处理装置和控制方法
公开(公告)号：US08655935B2
公开(公告)日：2014-02-18
申请号：US12047782
申请日：2008-03-13
申请人： Mikio Hondou , Ryuji Kan , Toshio Yoshida
发明人： Mikio Hondou , Ryuji Kan , Toshio Yoshida
IPC分类号： G06F1/02
CPC分类号： G06F7/548 , G06F1/02 , G06F7/483 , G06F7/5443
摘要： A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.
摘要翻译：一种处理装置，包括存储操作数数据的寄存器，读取存储在寄存器中的操作数数据的寄存器数据读取部，存储存储泰勒级数运算系数数据的系数表的系数表组存储部，读取使用泰勒级数的度数信息和系数表识别信息的系数表组存储部分的泰勒级数系数数据和使用由系数数据读取部分读取的系数数据执行泰勒级数操作的浮点乘法器，从寄存器读取的数据。

18. 发明授权

US07958338B2 Instruction execution control device and instruction execution control method 失效
标题翻译：指令执行控制装置和指令执行控制方法
公开(公告)号：US07958338B2
公开(公告)日：2011-06-07
申请号：US12591993
申请日：2009-12-07
申请人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
发明人： Yasunobu Akizuki , Toshio Yoshida , Tomohiro Tanaka , Ryuji Kan
IPC分类号： G06F9/38 , G06F9/52
CPC分类号： G06F9/3851 , G06F9/30123 , G06F9/30127 , G06F9/30141
摘要： An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.
摘要翻译：指令执行控制装置在同时多线程系统中操作多个线程。该装置具有针对每个线程的架构寄存器（22-0,22-1）和选择电路（32,24），当从寄存器文件（20）读取执行功能所需的操作数数据时，选择推进从注册文件（20）读取的线程。这使得能够在早期阶段选择体系结构寄存器，并且尽管用于选择架构寄存器的部分中的电路数量增加，但是由于要读取的线程的体系结构寄存器可以减少电路的布线量提前选择。

19. 发明申请

US20080228846A1 PROCESSING APPARATUS AND CONTROL METHOD THEREOF 有权
标题翻译：处理装置及其控制方法
公开(公告)号：US20080228846A1
公开(公告)日：2008-09-18
申请号：US12047782
申请日：2008-03-13
申请人： Mikio HONDOU , Ryuji Kan , Toshio Yoshida
发明人： Mikio HONDOU , Ryuji Kan , Toshio Yoshida
IPC分类号： G06F7/483
CPC分类号： G06F7/548 , G06F1/02 , G06F7/483 , G06F7/5443
摘要： A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.
摘要翻译：一种处理装置，包括存储操作数数据的寄存器，读取存储在寄存器中的操作数数据的寄存器数据读取部分，存储存储泰勒级数运算系数数据的系数表的系数表存储部分，读取使用泰勒级数的度数信息和系数表识别信息的系数表组存储部分的泰勒级数系数数据和使用由系数数据读取部分读取的系数数据执行泰勒级数操作的浮点乘法器，从寄存器读取的数据。

20. 发明授权

US07343478B2 Register window system and method that stores the next register window in a temporary buffer 失效
标题翻译：注册窗口系统和方法将下一个寄存器窗口存储在临时缓冲区中
公开(公告)号：US07343478B2
公开(公告)日：2008-03-11
申请号：US11333229
申请日：2006-01-18
申请人： Ryuji Kan , Hideo Yamashita , Toshio Yoshida
发明人： Ryuji Kan , Hideo Yamashita , Toshio Yoshida
IPC分类号： G06F9/44
CPC分类号： G06F9/30043 , G06F9/30127 , G06F9/3851
摘要： The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in the replacing buffer; and a control unit which transfers, if a window switching instruction is decoded at execution of the window switching instruction by the arithmetic operation unit, data of the register window which is to be specified by the current window pointer upon completion of execution of the window switching instruction, to the replacing buffer.
摘要翻译：本装置在采用无序指令执行方法的信息处理装置中减少硬件资源并提高数据读取吞吐量。该装置包括：算术运算单元，执行窗口切换指令和与存储在当前寄存器中的数据或保存在替换缓冲器中的数据有关的指令; 以及控制单元，如果在由算术运算单元执行窗口切换指令时对窗口切换指令进行了解码，则在完成窗口切换的执行完成后由当前窗口指针指定的寄存器窗口的数据指令，到替换缓冲区。

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