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11. 发明授权

US06852594B1 Two-step source side implant for improving source resistance and short channel effect in deep sub-0.18μm flash memory technology 有权
标题翻译：两级源端植入，用于提高深亚0.18微米闪存技术中的源极电阻和短沟道效应
公开(公告)号：US06852594B1
公开(公告)日：2005-02-08
申请号：US10053256
申请日：2002-01-18
申请人： Zhigang Wang , Yue-Song He , Richard Fastow
发明人： Zhigang Wang , Yue-Song He , Richard Fastow
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： Methods of forming flash memory EEPROM devices having lightly doped source region near the critical gate region and a heavily doped source region away from the critical gate region. In a first embodiment a first source mask is formed exposing source regions and portions of the gates and implanting n dopant ions, replacing the first source mask with a second source mask that exposes a portion of the source regions and implanting n+ dopant ions. In a second embodiment a source mask is formed exposing a portion of the source regions and implanting n+ dopant ions.
摘要翻译：形成具有在临界栅极区附近的轻掺杂源极区域和远离临界栅极区域的重掺杂源极区域的快闪存储器EEPROM器件的方法。在第一实施例中，形成第一源掩模，用于暴露源极区域和栅极的部分以及注入n个掺杂剂离子，用第二源极掩模代替第一源极掩模，第二源极掩模暴露出源区域的一部分并注入n +掺杂离子。在第二实施例中，形成暴露源区的一部分并注入n +掺杂离子的源掩模。

12. 发明授权

US06773990B1 Method for reducing short channel effects in memory cells and related structure 有权
标题翻译：减少存储单元短路效应的方法及相关结构
公开(公告)号：US06773990B1
公开(公告)日：2004-08-10
申请号：US10429150
申请日：2003-05-03
申请人： Richard Fastow , Yue-Song He , Kazuhiro Mizutani , Timothy Thurgate
发明人： Richard Fastow , Yue-Song He , Kazuhiro Mizutani , Timothy Thurgate
IPC分类号： H10L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.
摘要翻译：根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底中的隔离区域去除介电材料以暴露沟槽的步骤，其中沟槽位于第一源区域和第二源极之间区域，其中沟槽限定衬底中的侧壁。该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入N型掺杂剂，其中N型掺杂剂形成N +型区域。该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入P型掺杂剂，其中P型掺杂剂形成P型区域，并且其中P型区域位于N +型下方地区。

13. 发明授权

US06768683B1 Low column leakage flash memory array 失效
标题翻译：低列泄漏闪存阵列
公开(公告)号：US06768683B1
公开(公告)日：2004-07-27
申请号：US10095739
申请日：2002-03-12
申请人： Richard Fastow , Sameer Haddad
发明人： Richard Fastow , Sameer Haddad
IPC分类号： G11C1604
CPC分类号： G11C7/18 , G11C5/063 , G11C16/0483
摘要： The present memory includes a plurality of transistors laid out in a number of rows and columns. First and second series-connected transistors are included in a first column, and are connected between first and second bit lines and are respectively associated with first and second word lines. A region between the series-connected first and second transistors is connected to a first bit line. Third and fourth series-connected transistors are included in a second column, and are connected between the second bit line and a third bit line and are respectively associated with third and fourth word lines. A region between the series-connected third and fourth transistors is connected to a second bit line. The first, second, third and fourth transistors are respective parts of first, second, third and fourth rows of transistors.
摘要翻译：本存储器包括布置在多个行和列中的多个晶体管。第一和第二串联晶体管被包括在第一列中，并且连接在第一和第二位线之间，并且分别与第一和第二字线相关联。串联的第一和第二晶体管之间的区域连接到第一位线。第三和第四串联晶体管被包括在第二列中，并且连接在第二位线和第三位线之间，并且分别与第三和第四字线相关联。串联的第三和第四晶体管之间的区域连接到第二位线。第一，第二，第三和第四晶体管是第一，第二，第三和第四行晶体管的相应部分。

14. 发明授权

US06700201B1 Reduction of sector connecting line capacitance using staggered metal lines 有权
标题翻译：使用交错金属线路减少扇区连接线路电容
公开(公告)号：US06700201B1
公开(公告)日：2004-03-02
申请号：US10013902
申请日：2001-12-11
申请人： Richard Fastow , Yue-Song He , Sameer Haddad
发明人： Richard Fastow , Yue-Song He , Sameer Haddad
IPC分类号： H01L2348
CPC分类号： H01L27/105 , Y10S257/906
摘要： In a memory array, a plurality of sectors are included. Each sector includes a plurality of parallel bit lines which lie in a plane. Sector connecting lines connect the sectors. These sector connecting lines are parallel to each other and to the bit lines. The sector connecting lines include a first set of sector connecting lines which lie in a plane parallel to and adjacent and spaced from the plane of the bit lines, and a second set of sector connecting lines which lie in a plane parallel to and adjacent and spaced from the plane of the first set of sector connecting lines. When viewed across the sector, consecutive sector connecting lines lie in the two different planes thereof in alternating manner, i.e., the sector connecting lines are in a staggered relation.
摘要翻译：在存储器阵列中，包括多个扇区。每个扇区包括位于平面中的多个并行位线。扇区连接线连接扇区。这些扇形连接线彼此平行并且与位线平行。扇形连接线包括第一组扇形连接线，它们位于与位线的平面平行且相邻并与其间隔开的平面中;以及第二组扇形连接线，其位于平行于并相邻并间隔开的平面中从第一套扇形连接线的平面。当跨扇区观看时，连续的扇区连接线以交替方式位于其两个不同的平面中，即扇区连接线处于交错关系。

15. 发明授权

US06646914B1 Flash memory array architecture having staggered metal lines 有权
标题翻译：具有交错金属线的闪存阵列架构
公开(公告)号：US06646914B1
公开(公告)日：2003-11-11
申请号：US10096313
申请日：2002-03-12
申请人： Sameer Haddad , Richard Fastow
发明人： Sameer Haddad , Richard Fastow
IPC分类号： G11C1604
CPC分类号： G11C7/18 , G11C16/0416
摘要： A memory array includes a plurality of sets of transistors, each set including a pair of transistors in series. Each such pair of transistors is connected between a pair of adjacent bit lines. Each of the pair of transistors in each set is associated with a different one of an adjacent pair of word lines. The array is configured by providing substantially strait elongated source/drain regions in side-by-side, parallel relation. Each bit line has a zigzag configuration and connects to a pair of adjacent source/drain regions in alternating manner along the bit line length.
摘要翻译：存储器阵列包括多组晶体管，每组晶体管包括串联的一对晶体管。每对这样的晶体管连接在一对相邻的位线之间。每组中的每对晶体管与相邻的一对字线中的不同的一个相关联。该阵列通过以并排的平行关系提供基本上两条细长的源极/漏极区域来配置。每个位线具有之字形配置并且沿着位线长度交替地连接到一对相邻的源极/漏极区域。

16. 发明授权

US06400608B1 Accurate verify apparatus and method for NOR flash memory cells in the presence of high column leakage 有权
标题翻译：在存在高柱泄漏的情况下，NOR闪存单元的精确验证装置和方法
公开(公告)号：US06400608B1
公开(公告)日：2002-06-04
申请号：US09842288
申请日：2001-04-25
申请人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland
发明人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland
IPC分类号： G11C1134
CPC分类号： G11C16/3422 , G11C16/344 , G11C16/3445
摘要： A technique is provided for reducing column leakage in a flash EEPROM device during an erase verification process, thereby preventing false verifies. The technique has application in NOR arrays or other types of arrays in which a number of cells are connected in parallel. The technique operates by reducing the leakage of the unselected cells in parallel to the selected cell being verified, thereby preventing false verifies. The technique can also be used in conjunction with other techniques for reducing column leakage, such as soft programming, automatic programming disturb erase (APDE), or various other Vth compacting schemes.
摘要翻译：提供了一种在擦除验证过程中减少闪存EEPROM器件中的列泄漏的技术，从而防止虚假验证。该技术在NOR阵列或其他类型的阵列中的应用，其中多个单元并联连接。该技术通过减少未被选择的小区的泄漏与所验证的所选择的小区并行，从而防止虚假验证来进行操作。该技术还可以与减少列泄漏的其他技术结合使用，例如软编程，自动编程干扰擦除（APDE）或各种其他Vth压缩方案。

17. 发明授权

US06294430B1 Nitridization of the pre-ddi screen oxide 有权
标题翻译： ddi屏幕氧化物的氮化
公开(公告)号：US06294430B1
公开(公告)日：2001-09-25
申请号：US09495213
申请日：2000-01-31
申请人： Richard Fastow , Sameer S. Haddad , Daniel Sobek
发明人： Richard Fastow , Sameer S. Haddad , Daniel Sobek
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/3144 , H01L29/511 , H01L29/7883 , Y10S438/923
摘要： A flash memory device and a method of manufacturing the flash memory device having high reliability in which a gate stack is formed on a tunnel oxide formed on a substrate and a layer of oxide is formed on the surfaces of the gate stack and exposed surfaces of the substrate. Nitrogen is diffused into the layer of oxide.
摘要翻译：闪存器件和制造具有高可靠性的闪速存储器件的方法，其中栅极堆叠形成在形成在衬底上的隧道氧化物上，并且氧化物层形成在栅极堆叠的表面上，基质。氮气扩散到氧化物层中。

18. 发明授权

US06198664B1 APDE scheme for flash memory application 有权
标题翻译：用于闪存应用的APDE方案
公开(公告)号：US06198664B1
公开(公告)日：2001-03-06
申请号：US09495215
申请日：2000-01-31
申请人： Richard Fastow
发明人： Richard Fastow
IPC分类号： G11C1100
CPC分类号： G11C16/3409 , G11C16/3404 , G11C16/3445
摘要： A method for erasing a flash EEPROM device that includes a plurality of memory cells. The plurality of memory cells is erase verified and an erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle repeats until all cells verify as erased and a flag is set to NO. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached and the flag is set to YES. This cycle repeats until all cells verify as not being overerased. If it is determined after the overerase verification step that the flag is set to YES, the plurality of memory cells is again erase verified and the procedure repeats. If it is determined after the overerase verification step that the flag is set to NO, the erase procedure is considered finished.
摘要翻译：一种用于擦除包括多个存储器单元的快闪EEPROM器件的方法。多个存储器单元被擦除验证，并且如果存在未存储的存储器单元并且存储器单元再次被擦除验证，则将擦除脉冲施加到存储器单元。重复此循环，直到所有单元格都被清除为止，并将标志设置为NO。多个存储器单元被过度验证，并且过载修正脉冲被施加到连接过度存储器单元的位线上，该标志被设置为“是”。这个循环重复，直到所有的单元格都被验证为没有过高。如果在过度认证步骤之后确定标志被设置为“是”，则多个存储器单元再次被擦除验证，并且重复该过程。如果在高过程验证步骤之后确定标志设置为NO，则认为擦除过程已完成。

19. 发明授权

US08896048B1 Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors 有权
标题翻译：间隔物形成后源侧注入的装置和方法，以减少金属氧化物半导体场效应晶体管的短沟道效应
公开(公告)号：US08896048B1
公开(公告)日：2014-11-25
申请号：US10861581
申请日：2004-06-04
申请人： Richard Fastow , Zhigang Wang , Yue-Song He , Kazuhiro Mizutani , Pavel Fastenko
发明人： Richard Fastow , Zhigang Wang , Yue-Song He , Kazuhiro Mizutani , Pavel Fastenko
IPC分类号： H01L29/76
CPC分类号： H01L29/66659 , H01L29/66825 , H01L29/7881
摘要： The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.
摘要翻译：本发明提供一种制造用于减少短沟道效应的金属氧化物半导体场效应晶体管（MOSFET）的装置和方法。 MOSFET包括半导体衬底，形成在半导体衬底上方的栅极堆叠，形成在栅极堆叠的漏极侧的漏极侧壁间隔物，形成在栅极堆叠的源极侧的源极侧壁隔离物，以及源极和漏极地区。源极区域形成在源极侧的半导体衬底中，并且通过源极侧壁间隔物对齐以在源极区域和漏极区域之间延伸有效沟道长度。漏极区域形成在半导体衬底的漏极侧，并且通过漏极侧壁间隔物排列以进一步延长有效沟道长度。

20. 发明授权

US08818802B2 Real-time data pattern analysis system and method of operation thereof 有权
标题翻译：实时数据模式分析系统及其操作方法
公开(公告)号：US08818802B2
公开(公告)日：2014-08-26
申请号：US12852970
申请日：2010-08-09
申请人： Richard Fastow , Qamrul Hasan
发明人： Richard Fastow , Qamrul Hasan
IPC分类号： G10L15/00
CPC分类号： G10L15/063 , G06K9/00979 , G10L15/02 , G10L15/14 , G10L15/28 , G10L2015/025
摘要： A method for real-time data-pattern analysis. The method includes receiving and queuing at least one data-pattern analysis request by a data-pattern analysis unit controller. At least one data stream portion is also received and stored by the data-pattern analysis unit controller, each data stream portion corresponding to a received data-pattern analysis request. Next, a received data-pattern analysis request is selected by the data-pattern analysis unit controller along with a corresponding data stream portion. A data-pattern analysis is performed based on the selected data-pattern analysis request and the corresponding data stream portion, wherein the data-pattern analysis is performed by one of a plurality of data-pattern analysis units.
摘要翻译：一种用于实时数据模式分析的方法。该方法包括由数据模式分析单元控制器接收和排队至少一个数据模式分析请求。至少一个数据流部分也被数据模式分析单元控制器接收和存储，每个数据流部分对应于接收的数据模式分析请求。接下来，数据模式分析单元控制器与对应的数据流部分一起选择接收的数据模式分析请求。基于选择的数据模式分析请求和对应的数据流部分执行数据模式分析，其中数据模式分析由多个数据模式分析单元之一执行。

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