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1. 发明授权

US07644226B1 System and method for maintaining RAM command timing across phase-shifted time domains 有权
标题翻译：用于在相移时间域上维护RAM命令定时的系统和方法
公开(公告)号：US07644226B1
公开(公告)日：2010-01-05
申请号：US11642412
申请日：2006-12-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan
IPC分类号： G06F12/00
CPC分类号： G06F13/1668
摘要： According to one exemplary embodiment, a RAM employing system includes a RAM and a RAM controller coupled to the RAM. The RAM employing system further includes a command queue, which is configured to receive time encoded RAM commands from the RAM controller. The RAM is configured to retrieve, decode, and execute each of the time encoded RAM commands in the command queue.
摘要翻译：根据一个示例性实施例，RAM采用系统包括RAM和耦合到RAM的RAM控制器。 RAM采用系统还包括命令队列，其被配置为从RAM控制器接收时间编码的RAM命令。 RAM被配置为在命令队列中检索，解码和执行每个时间编码的RAM命令。

2. 发明授权

US07639768B1 Method for improving performance in a mobile device 有权
标题翻译：提高移动设备性能的方法
公开(公告)号：US07639768B1
公开(公告)日：2009-12-29
申请号：US11414845
申请日：2006-05-01
申请人： Qamrul Hasan , Jeremy Mah , Stephan Rosner
发明人： Qamrul Hasan , Jeremy Mah , Stephan Rosner
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： G06F13/4243 , G06F13/1657 , Y02D10/14 , Y02D10/151
摘要： In the operation of a mobile device (such as a cellular telephone or a PDA, i.e. Personal Digital Assistant), which mobile device includes a mobile terminal and a memory module, certain operational signals of the mobile device are multiplexed and demultiplexed, resulting in efficient device bus utilization and reduced device pin count.
摘要翻译：在移动设备（例如蜂窝电话或PDA，即个人数字助理）的操作中，哪个移动设备包括移动终端和存储器模块，移动设备的某些操作信号被多路复用和解复用，导致有效器件总线利用率和减少器件引脚数。

3. 发明申请

US20070239918A1 Multi media card with high storage capacity 有权
标题翻译：具有高存储容量的多媒体卡
公开(公告)号：US20070239918A1
公开(公告)日：2007-10-11
申请号：US11400902
申请日：2006-04-10
申请人： Qamrul Hasan , Jeremy Mah , Stephan Rosner , Roger Isaac
发明人： Qamrul Hasan , Jeremy Mah , Stephan Rosner , Roger Isaac
IPC分类号： H05K7/10 , G06F12/00
CPC分类号： G06F12/0623 , G06F2212/2022
摘要： A multi media card includes a plurality of memory modules and an extraneous command decoder. The extraneous command decoder decodes a predetermined command for determining a selected memory module to be accessed from the plurality of memory modules, when a predetermined bit of the predetermined command is set to a predetermined logic level.
摘要翻译：多媒体卡包括多个存储器模块和外部命令解码器。当预定命令的预定位被设置为预定逻辑电平时，无关命令解码器解码用于确定要从多个存储器模块访问的所选存储器模块的预定命令。

4. 发明授权

US08700830B2 Memory buffering system that improves read/write performance and provides low latency for mobile systems 有权
标题翻译：内存缓冲系统，可提高读/写性能，并为移动系统提供低延迟
公开(公告)号：US08700830B2
公开(公告)日：2014-04-15
申请号：US11943544
申请日：2007-11-20
申请人： Qamrul Hasan , Stephan Rosner , Roger Dwain Isaac
发明人： Qamrul Hasan , Stephan Rosner , Roger Dwain Isaac
IPC分类号： G06F13/12
CPC分类号： G06F13/161 , G06F13/1605 , G06F13/1626 , G06F13/1642 , G06F13/1673 , G06F13/1694 , G06F13/372 , G06F13/4282
摘要： A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.
摘要翻译：公开了一种存储器缓冲系统，其通过用于链式架构中的存储器元件的仲裁方案仲裁总线所有权。统一的主机内存控制器仲裁总线所有权，将其传输到统一的内存缓冲区和链式体系结构中的其他缓冲区。该系统在具有链路架构和并行架构中的总线的通信系统中使用。

5. 发明授权

US08140778B1 Apparatus and method for data capture using a read preamble 有权
标题翻译：使用读取前同步码进行数据采集的装置和方法
公开(公告)号：US08140778B1
公开(公告)日：2012-03-20
申请号：US12880018
申请日：2010-09-10
申请人： Qamrul Hasan , Clifford Alan Zitlaw , Stephan Rosner , Dubois Sylvain
发明人： Qamrul Hasan , Clifford Alan Zitlaw , Stephan Rosner , Dubois Sylvain
IPC分类号： G06F13/00 , G06F13/28 , H04L7/00
CPC分类号： G11C7/1093 , G11C29/022 , G11C29/028
摘要： A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and a valid clock calculation component. The DLL component is arranged to provide clock signals. The data sampling component is arranged to receive a serial data signal that includes a read preamble, where the read preamble includes a training pattern, and to sample the serial data signal with each of the clock signals. The comparison component is arranged to compare each of the sampled data signals with an expected training pattern. The valid clock calculation component is arranged to, based on the comparisons, select one of the clock signals as the valid clock signal for locking the DLL component to.
摘要翻译：提供数据采集装置。数据采集装置包括数据采集装置控制器和数据采集部件。数据捕获装置被配置为发送突发读取命令。每个数据捕获组件包括DLL组件，数据采样组件，比较组件和有效时钟计算组件。 DLL组件被设置成提供时钟信号。数据采样部件被布置为接收包括读取前置码的串行数据信号，其中读取前同步码包括训练模式，并且利用每个时钟信号对串行数据信号进行采样。比较部件被布置为将每个采样数据信号与预期的训练模式进行比较。有效时钟计算部件被配置为基于比较，选择一个时钟信号作为用于锁定DLL组件的有效时钟信号。

6. 发明授权

US07840900B1 Replacing reset pin in buses while guaranteeing system recovery 有权
标题翻译：在保证系统恢复的同时，更换总线中的复位引脚
公开(公告)号：US07840900B1
公开(公告)日：2010-11-23
申请号：US12433499
申请日：2009-04-30
申请人： Stephan Rosner , Qamrul Hasan , Roger Dwain Isaac
发明人： Stephan Rosner , Qamrul Hasan , Roger Dwain Isaac
IPC分类号： G06F15/00 , G06F13/00
CPC分类号： G06F1/24 , G06F1/22 , G06F11/0757
摘要： Systems and methods are disclosed that replace a separate reset pin in a bus with a reset command that guarantees a system recovery. The system comprises a host component circuitry residing on a first chip and a client component circuitry residing on a second, different chip. A bus connects the host component circuitry to the client component circuitry. The host component circuitry is configured to transfer an initial client value associated with a client component time period to the client component circuitry over the bus on a periodic time basis. The periodic time basis is dictated by a host component time period and the client component time period is greater than the host component time period. The client component circuitry is configured to initiate a reset procedure if the client component time period expires which indicates that the initial client value was not received at a next time on the periodic time basis dictated by the host component time period.
摘要翻译：公开了一种系统和方法，用一个复位命令来代替总线中的一个单独的复位引脚，保证系统恢复。该系统包括驻留在第一芯片上的主机组件电路和驻留在第二不同芯片上的客户端组件电路。总线将主机组件电路连接到客户端组件电路。主机组件电路被配置为以周期性的时间通过总线将与客户端组件时间段相关联的初始客户端值传送到客户端组件电路。周期时间基准由主机组件时间段指定，并且客户端组件时间段大于主机组件时间段。如果客户端组件时间段到期，则客户端组件电路被配置为启动重置过程，其指示在由主机组件时间段指定的周期时间基础上的下一次未接收到初始客户端值。

7. 发明申请

US20080177931A1 BYTE MASK COMMAND FOR MEMORIES 有权
公开(公告)号：US20080177931A1
公开(公告)日：2008-07-24
申请号：US11625158
申请日：2007-01-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F13/4239
摘要： A system is presented that facilitates masking data in write data bound for a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends a write command and write data to the memory array and the memory array updates data contained therein based upon the write command and write data. If the write operation requires a byte mask, the controller sends a byte mask command via a command bus linking the controller and the memory array. Accordingly, separate and dedicated byte mask pins or bus is not necessary to convey byte mask information.
摘要翻译：提出了一种有助于屏蔽存储器件写入数据的数据的系统。该系统包含存储器控制器和通信地耦合到存储器控制器的存储器阵列。存储器控制器发送写命令并将数据写入存储器阵列，并且存储器阵列基于写命令和写数据来更新其中包含的数据。如果写操作需要一个字节掩码，则控制器通过链接控制器和存储器阵列的命令总线发送字节掩码命令。因此，不需要单独和专用的字节掩码引脚或总线来传送字节掩码信息。

8. 发明授权

US08230154B2 Fully associative banking for memory 有权
标题翻译：充分结合银行记忆
公开(公告)号：US08230154B2
公开(公告)日：2012-07-24
申请号：US11625150
申请日：2007-01-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
IPC分类号： G06F12/06
CPC分类号： G06F9/5016 , G11C15/00 , G11C16/26
摘要： A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.
摘要翻译：提供了一种促进存储器件中的读取访问的系统。该系统包括存储与一个或多个软件线程相关联的高阶地址的多个行地址缓冲器。系统还包括多个行数据缓冲器。行数据缓冲器各自与至少一个行地址缓冲器相关联，并且在行地址缓冲器的高位地址的范围内存储行数据。该系统通过限制与上下文切换相关的延迟来增加存储器件性能。多个行地址缓冲器和行数据缓冲器使得软件线程能够与一个或多个缓冲器相关联，并且尽管上下文切换来维持有效的后续存储器访问。

9. 发明申请

US20090132736A1 MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS 有权
标题翻译：改善阅读/写入性能并为移动系统提供低延迟的内存缓冲系统
公开(公告)号：US20090132736A1
公开(公告)日：2009-05-21
申请号：US11943544
申请日：2007-11-20
申请人： Qamrul Hasan , Stephan Rosner , Roger Dwain Isaac
发明人： Qamrul Hasan , Stephan Rosner , Roger Dwain Isaac
IPC分类号： G06F13/00
CPC分类号： G06F13/161 , G06F13/1605 , G06F13/1626 , G06F13/1642 , G06F13/1673 , G06F13/1694 , G06F13/372 , G06F13/4282
摘要： A memory buffering system is disclosed that arbitrates bus ownership through all arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.
摘要翻译：公开了一种存储器缓冲系统，其通过用于链式架构中的存储器元件的所有仲裁方案仲裁总线所有权。统一的主机内存控制器仲裁总线所有权，将其传输到统一的内存缓冲区和链式体系结构中的其他缓冲区。该系统在具有链路架构和并行架构中的总线的通信系统中使用。

10. 发明申请

US20080177930A1 FULLY ASSOCIATIVE BANKING FOR MEMORY 有权
标题翻译：全面的联想银行记忆
公开(公告)号：US20080177930A1
公开(公告)日：2008-07-24
申请号：US11625150
申请日：2007-01-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
IPC分类号： G06F12/02
CPC分类号： G06F9/5016 , G11C15/00 , G11C16/26
摘要： A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.
摘要翻译：提供了一种促进存储器件中的读取访问的系统。该系统包括存储与一个或多个软件线程相关联的高阶地址的多个行地址缓冲器。系统还包括多个行数据缓冲器。行数据缓冲器各自与至少一个行地址缓冲器相关联，并且在行地址缓冲器的高位地址的范围内存储行数据。该系统通过限制与上下文切换相关的延迟来增加存储器件性能。多个行地址缓冲器和行数据缓冲器使得软件线程能够与一个或多个缓冲器相关联，并且尽管上下文切换来维持有效的后续存储器访问。

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