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11. 发明申请

WO1996010266A1 FIXED VALUE STORAGE CELL ARRANGEMENT AND METHOD OF PRODUCING THE SAME 审中-公开
标题翻译： FIXED VALUE存储器单元装置和方法及其
公开(公告)号：WO1996010266A1
公开(公告)日：1996-04-04
申请号：PCT/DE1995001262
申请日：1995-09-14
申请人： SIEMENS AKTIENGESELLSCHAFT , KRAUTSCHNEIDER, Wolfgang , RISCH, Lothar , HOFMANN, Franz , RÖSNER, Wolfgang
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L27/112
CPC分类号： H01L27/11273 , H01L27/112
摘要： The invention concerns a fixed value storage cell arrangement comprising, in a substrate (21) of semiconductor material, storage cells each having a vertical MOS transistor. The various logical values (zero, one) are brought about by gate dielectrics (27, 28) of different thicknesses. The storage cell arrangement can be produced in particular in a silicon substrate using few process steps and a high packing density. The storage cell arrangement and a readout control circuit can thus be produced integrally.
摘要翻译：只读存储单元阵列包括存储器单元，每一个都具有垂直MOS晶体管，其中所述的各种逻辑值（零个，一个）由不同厚度的栅极介质（27，28）可在基板（21）来实现的半导体材料。存储单元阵列可特别地产生具有很少的工艺步骤和高堆积密度的硅衬底。所述存储器单元阵列和控制电路，用于读出在这里可以制备一体化。

12. 发明申请

WO0106542A3 METHOD FOR PRODUCING A VERTICAL SEMICONDUCTOR TRANSISTOR COMPONENT ELEMENT AND A VERTICAL SEMICONDUCTOR TRANSISTOR COMPONENT 审中-公开
标题翻译：制造垂直半导体晶体管组件和垂直半导体晶体管组件的方法
公开(公告)号：WO0106542A3
公开(公告)日：2001-07-19
申请号：PCT/DE0002316
申请日：2000-07-17
申请人： INFINEON TECHNOLOGIES AG , SCHULZ THOMAS , ROESNER WOLFGANG , FRANOSCH MARTIN , SCHAEFER HERBERT , RISCH LOTHAR , AEUGLE THOMAS
发明人： SCHULZ THOMAS , ROESNER WOLFGANG , FRANOSCH MARTIN , SCHAEFER HERBERT , RISCH LOTHAR , AEUGLE THOMAS
IPC分类号： H01L21/335 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/76 , H01L51/00 , H01L51/05 , H01L51/30
CPC分类号： B82Y10/00 , H01L21/823487 , H01L27/088 , H01L29/66439 , H01L29/66666 , H01L29/7613 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： According to the invention, a double gate MOSFET semiconductor layer structure is formed on a substrate (1). This structure is comprised of a first and of a second gate electrode (10A, 10B) between which a semiconductor channel layer zone (4A) is embedded, and of a source region (2A) and a drain region (2B) which are arranged on opposite faces of the semiconductor channel layer zone (4A). At least one additional semiconductor channel layer zone (6A) is provided on one of the gate electrodes (10B). The faces of the at least one additional semiconductor channel layer zone are also contacted by the source region (2A) and drain region (2B).
摘要翻译：在衬底（1）上构建双栅MOSFET半导体层结构。这在半导体沟道层区的相对的端面由第一和在其之间的半导体沟道层区域（4A）被嵌入第二栅电极（10A，10B），以及源极（2A）和漏极区域（2b）中的（4A）被布置。在其中一个栅电极（10B）上提供至少一个另外的半导体沟道层区域（6A），其端面同样与源极（2A）和漏极区域（2B）接触。

13. 发明申请

WO0137342A2 CIRCUIT ARRANGEMENT COMPRISING AT LEAST ONE CAPACITOR AND AT LEAST ONE TRANSISTOR CONNECTED THERETO 审中-公开
标题翻译：与至少一个电容器和至少一个相关联的晶体管电路安排
公开(公告)号：WO0137342A2
公开(公告)日：2001-05-25
申请号：PCT/DE0003982
申请日：2000-11-14
申请人： INFINEON TECHNOLOGIES AG , HOFMANN FRANZ , RISCH LOTHAR , ROESNER WOLFGANG , SCHLOESSER TILL
发明人： HOFMANN FRANZ , RISCH LOTHAR , ROESNER WOLFGANG , SCHLOESSER TILL
IPC分类号： H01L21/336 , H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/78 , H01L29/786 , H01L25/00
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10891 , H01L27/1203
摘要： The invention relates to a transistor that is provided with a first source/drain area (S/D1), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D1). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D1) are arranged in the insulating area. The second source/drain area (S/D2) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.
摘要翻译：该晶体管的第一源极/漏极区（S / D1），其上的沟道区相邻的（KA），一个与其相邻的第二源极/漏极区（S / D2），栅极电介质和栅极电极。所述电容器的第一电容器电极（SP）被连接到所述第一源极/漏极区（S / D1）。绝缘结构完全围绕的电路的绝缘区域。在至少所述第一电容器电极（SP）和所述第一源极的绝缘区/漏极区（S / D1）被布置，而第二源极/漏极区（S / D2）和所述电容器的第二电容器电极上的绝缘外排列区域。因为绝缘结构的电荷不会丢失由于从充电和放电电容器之间的第一电容器电极（SP）的漏电流。在沟道区中的隧穿势垒（T），其设置（KA），是在绝缘结构的部分。电容器电介质（KD），（SP）分离所述第二电容器电极的第一电容器电极，在绝缘结构的部分。

14. 发明申请

WO1997002599A1 METHOD OF PRODUCING A READ-ONLY STORAGE CELL ARRANGEMENT 审中-公开
标题翻译：一种用于生产硬存储器单元装置
公开(公告)号：WO1997002599A1
公开(公告)日：1997-01-23
申请号：PCT/DE1996001117
申请日：1996-06-25
申请人： SIEMENS AKTIENGESELLSCHAFT , HOFMANN, Franz , RÖSNER, Wolfgang , KRAUTSCHNEIDER, Wolfgang , RISCH, Lothar
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L21/8247
CPC分类号： H01L27/11517 , H01L27/115
摘要： In order to produce a read-only storage cell arrangement, strip-shaped grooves are etched in a semiconductor substrate, storage cells each having a vertical MOS transistor with a floating gate (11) being formed on the flanks of these grooves. The source/drain areas of the MOS transistors are produced as strip-shaped doped areas at the base of the grooves (7) and between adjacent grooves (7) in a self-aligning manner using only one mask. The widths of the grooves (7) and the spacings between them are preferably identical such that the storage cell arrangement can be produced with a space requirement of 2F (F: minimum size of the structure).
摘要翻译：为了产生在半导体衬底中的只读存储单元阵列，条状蚀刻沟槽，在它们的边缘上形成各具有与浮置栅极（11）的垂直MOS晶体管的存储单元。所述MOS晶体管的源极/漏极区通过仅使用一个掩模制作在沟槽（7）的底部上的带状掺杂区域和相邻的沟槽（7）自对准方式之间。宽度和沟槽（7）的间距优选是相等的，使得具有2F的空间需求的存储单元阵列<2>：是可实现的（F最小特征尺寸）。

15. 发明申请

WO1996013064A1 PROCESS FOR PRODUCING A READ-ONLY STORAGE CELL ARRANGEMENT WITH VERTICAL MOS TRANSISTORS 审中-公开
标题翻译：方法用于生产具有垂直MOS晶体管的一道存储器单元装置
公开(公告)号：WO1996013064A1
公开(公告)日：1996-05-02
申请号：PCT/DE1995001365
申请日：1995-10-05
申请人： SIEMENS AKTIENGESELLSCHAFT , RISCH, Lothar , HOFMANN, Franz , RÖSNER, Wolfgang , KRAUTSCHNEIDER, Wolfgang
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L21/8246
CPC分类号： H01L27/112
摘要： To produce a read-only storage cell arrangement with first storage cells comprising a vertical MOS transistor and second storage cells comprising no vertical MOS transistors, holes (13) are etched in a silicon substrate (1) with a sequence of layers corresponding to source (1), channel (2) and drain (11) for the first storage cells, having a gate dielectric (14) and a gate electrode (15a). Insulation pits (7) at a spacing of preferably their width are produced to isolate neighbouring storage cells.
摘要翻译：为了生产具有包括垂直MOS晶体管的第一存储单元不包括垂直MOS晶体管的只读存储单元结构中，和第二存储单元根据所述源（1），通道（2）和漏区是在硅衬底（1）的层序列被提供（11）蚀刻（13），用于与栅极电介质（14）和栅电极（15A）的第一存储器单元孔。对于（7），产生相邻的存储器单元的绝缘沟槽隔离，该距离优选地等于其宽度。

16. 发明申请

WO1995031828A1 GAIN CELL DRAM STRUCTURE AND PROCESS FOR PRODUCING THE SAME 审中-公开
标题翻译：增益单元DRAM结构及其制造方法
公开(公告)号：WO1995031828A1
公开(公告)日：1995-11-23
申请号：PCT/EP1995001656
申请日：1995-05-02
申请人： SIEMENS AKTIENGESELLSCHAFT , KRAUTSCHNEIDER, Wolfgang , RISCH, Lothar , HOFMANN, Franz
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L27/108
CPC分类号： H01L27/10844 , H01L27/0629 , H01L27/108
摘要： An arrangement with dynamic MOS transistor gain memory cells has a selection transistor, a memory transistor and a diode structure. The selection transistor and the memory transistor are interconnected in series through a common node (20) and the diode structure (11) is connected between the common node and the gate electrode (10) of the memory transistor. In order to produce such an arrangement, the selection transistor and the memory transistor are realized as vertical MOS transistors. A vertical series of correspondingly doped zones (2, 3, 4) in which trenches (5, 6) are generated and which are provided with gate dielectric (7, 8) and gate electrode (9, 10) is further produced in particular by LPCVD epitaxy or by molecular-beam epitaxy. Insulating structures are formed by trenches (14, 17, 19).
摘要翻译：用于产生具有自放大动态MOS晶体管的存储单元的布置中，每一个都包括所述公共节点之间的选择晶体管，存储晶体管和一个二极管结构，其中通过共同的节点（20）的选择晶体管和存储晶体管串联连接，二极管结构（11）和所述栅电极（10）被连接在存储晶体管中，选择晶体管和存储晶体管实现为垂直MOS晶体管。为此（4×2，3）是特别LPCVD外延或由对应于在沟槽中产生掺杂区域的垂直序列（5，6）产生的分子束外延和栅极电介质（7，8）被提供并且栅极电极（10 9），通过沟槽（14，17，19）是绝缘的产生的结构。

17. 发明申请

WO1995028741A1 MICRO-ELECTRONIC COMPONENT AND PROCESS FOR MAKING IT 审中-公开
标题翻译： MICRO电子元件与方法研究
公开(公告)号：WO1995028741A1
公开(公告)日：1995-10-26
申请号：PCT/DE1995000448
申请日：1995-04-04
申请人： SIEMENS AKTIENGESELLSCHAFT , GOSSNER, Harald , EISELE, Ignaz , RISCH, Lothar , HAMMERL, Erwin
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L29/10
CPC分类号： H01L29/127 , B82Y10/00 , H01L21/02381 , H01L21/02532 , H01L21/02609 , H01L21/02639 , H01L29/1054 , H01L29/125 , H01L29/66439 , H01L29/78
摘要： A silicon MOS component has a surface structure (6) in the gate region (10) with edges and/or points at which, when a gate voltage is applied, preferably inversion regions are formed which are suitable as quantum wires or quantum dots. The surface structure is produced especially as silicon pyramids (6) by local molecular beam epitaxy.
摘要翻译：在硅MOS技术的器件具有栅极区（10）的表面结构（6）的边缘和/或点，其中，当栅极电压优选反转区域，这是因为量子线或量子点有用发展。该表面结构是特别是作为通过局部分子束外延由硅制成的锥体（6）制成。

18. 发明申请

WO1992001287A1 DEVICE WITH SELF-AMPLIFYING DYNAMIC MOS TRANSISTOR STORAGE CELLS 审中-公开
标题翻译：具有自放大动态MOS晶体管存储单元的器件
公开(公告)号：WO1992001287A1
公开(公告)日：1992-01-23
申请号：PCT/DE1991000502
申请日：1991-06-18
申请人： SIEMENS AKTIENGESELLSCHAFT , KRAUTSCHNEIDER, Wolfgang , RISCH, Lothar , LAU, Klaus
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G11C05/00
CPC分类号： G11C11/405 , G11C5/005 , G11C11/404 , H01L27/108
摘要： The invention concerns a device with self-amplifying dynamic MOS transistor cells each with an MOS selector transistor (AT), the gate of which is connected to a word line (WL), and an MOS storage transistor (ST) at the gate of which is applied a capacitor (C) for charge storage. This self-amplifying storage cell can be described into and read out with only one bit line (BL) and one word line (WL). The two transistors (AT and ST) are connected in series and a shared drain source region (DS) is connected to the gate electrode (GST) of the control transistor via a voltage-dependent resistor (VR). The main advantages of the invention are that the line geometry can be scaled without reducing the charge quantity (Q) which can be read out from the bit line (BL), that the charge quantity (Q) which can be read out is greater than the charge stored in the capacitor (C) operative at the gate of the storage transistor and that the two MOS transistors (AT and ST) are fairly easy to make.
摘要翻译：本发明涉及具有自放大动态MOS晶体管单元的器件，每个具有MOS选择晶体管（AT），其栅极连接到字线（WL），其栅极处的MOS存储晶体管（ST）施加电容器（C）用于电荷存储。该自放大存储单元可以仅用一个位线（BL）和一个字线（WL）进行描述和读出。两个晶体管（AT和ST）串联连接，并且共用漏极源极区（DS）经由电压依赖电阻（VR）连接到控制晶体管的栅极（GST）。本发明的主要优点在于可以缩放线几何形状，而不会减小可从位线（BL）读出的电荷量（Q），即可读出的电荷量（Q）大于存储在存储晶体管的栅极处的电容器（C）中存储的电荷以及两个MOS晶体管（AT和ST）相当容易制造。

19. 发明申请

WO1990010952A1 OVERVOLTAGE PROTECTION CIRCUIT FOR MOS COMPONENTS 审中-公开
标题翻译： MOS组件的过电压保护电路
公开(公告)号：WO1990010952A1
公开(公告)日：1990-09-20
申请号：PCT/DE1990000027
申请日：1990-01-18
申请人： SIEMENS AKTIENGESELLSCHAFT , TERLETZKI, Hartmud , RISCH, Lothar
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L27/02
CPC分类号： H01L27/0266
摘要： The invention relates to an overvoltage protection circuit for MOS components consisting of a resistor (R), a field oxide transistor (FOX) and a thin oxide transistor (DOX). The breakdown of the parasitic dipole transistor inside the field oxide transistor is optimised so that the latter can with certainty leak off all the energy of an overvoltage pulse against the reference potential (VSS). The measures described reduce the thermal damage known as 'spiking' which can cause the MOS component to break down.

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