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1. 发明申请

WO1992001287A1 DEVICE WITH SELF-AMPLIFYING DYNAMIC MOS TRANSISTOR STORAGE CELLS 审中-公开
标题翻译：具有自放大动态MOS晶体管存储单元的器件
公开(公告)号：WO1992001287A1
公开(公告)日：1992-01-23
申请号：PCT/DE1991000502
申请日：1991-06-18
申请人： SIEMENS AKTIENGESELLSCHAFT , KRAUTSCHNEIDER, Wolfgang , RISCH, Lothar , LAU, Klaus
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G11C05/00
CPC分类号： G11C11/405 , G11C5/005 , G11C11/404 , H01L27/108
摘要： The invention concerns a device with self-amplifying dynamic MOS transistor cells each with an MOS selector transistor (AT), the gate of which is connected to a word line (WL), and an MOS storage transistor (ST) at the gate of which is applied a capacitor (C) for charge storage. This self-amplifying storage cell can be described into and read out with only one bit line (BL) and one word line (WL). The two transistors (AT and ST) are connected in series and a shared drain source region (DS) is connected to the gate electrode (GST) of the control transistor via a voltage-dependent resistor (VR). The main advantages of the invention are that the line geometry can be scaled without reducing the charge quantity (Q) which can be read out from the bit line (BL), that the charge quantity (Q) which can be read out is greater than the charge stored in the capacitor (C) operative at the gate of the storage transistor and that the two MOS transistors (AT and ST) are fairly easy to make.
摘要翻译：本发明涉及具有自放大动态MOS晶体管单元的器件，每个具有MOS选择晶体管（AT），其栅极连接到字线（WL），其栅极处的MOS存储晶体管（ST）施加电容器（C）用于电荷存储。该自放大存储单元可以仅用一个位线（BL）和一个字线（WL）进行描述和读出。两个晶体管（AT和ST）串联连接，并且共用漏极源极区（DS）经由电压依赖电阻（VR）连接到控制晶体管的栅极（GST）。本发明的主要优点在于可以缩放线几何形状，而不会减小可从位线（BL）读出的电荷量（Q），即可读出的电荷量（Q）大于存储在存储晶体管的栅极处的电容器（C）中存储的电荷以及两个MOS晶体管（AT和ST）相当容易制造。

2. 发明申请

WO1996029739A1 READ-ONLY STORAGE CELL ARRANGEMENT AND PROCESS FOR ITS PRODUCTION 审中-公开
标题翻译： FIXED VALUE存储器单元装置和方法及其
公开(公告)号：WO1996029739A1
公开(公告)日：1996-09-26
申请号：PCT/DE1996000380
申请日：1996-03-04
申请人： SIEMENS AKTIENGESELLSCHAFT , KRAUTSCHNEIDER, Wolfgang , RISCH, Lothar , HOFMANN, Franz
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L27/112
CPC分类号： H01L27/1126 , H01L27/112
摘要： A read-only storage cell arrangement comprises a plurality of individual storage cells, each comprising an MOS transistor and which are arranged in parallel lines. Adjacent lines run alternately at the bottom of longitudinal grooves (6) and between adjacent longitudinal grooves (6) and are insulated from one another. The read-only storage cell arrangement can be made by self-adjusting process stages requiring an area of 2 F per storage cell (F: minimum structural size).
摘要翻译：包括多个单独的存储单元的只读存储器单元装置的每一个包括MOS晶体管和并联布置的行。相邻排在每种情况下交替延伸的纵向沟槽（6）的底部和相邻的纵向沟槽（6）之间，并且彼此绝缘。只读存储器单元装置是通过用每2 F <2>的存储器单元的面积需求自对准工艺步骤（F：最小特征尺寸）以产生。

3. 发明申请

WO1996010266A1 FIXED VALUE STORAGE CELL ARRANGEMENT AND METHOD OF PRODUCING THE SAME 审中-公开
标题翻译： FIXED VALUE存储器单元装置和方法及其
公开(公告)号：WO1996010266A1
公开(公告)日：1996-04-04
申请号：PCT/DE1995001262
申请日：1995-09-14
申请人： SIEMENS AKTIENGESELLSCHAFT , KRAUTSCHNEIDER, Wolfgang , RISCH, Lothar , HOFMANN, Franz , RÖSNER, Wolfgang
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L27/112
CPC分类号： H01L27/11273 , H01L27/112
摘要： The invention concerns a fixed value storage cell arrangement comprising, in a substrate (21) of semiconductor material, storage cells each having a vertical MOS transistor. The various logical values (zero, one) are brought about by gate dielectrics (27, 28) of different thicknesses. The storage cell arrangement can be produced in particular in a silicon substrate using few process steps and a high packing density. The storage cell arrangement and a readout control circuit can thus be produced integrally.
摘要翻译：只读存储单元阵列包括存储器单元，每一个都具有垂直MOS晶体管，其中所述的各种逻辑值（零个，一个）由不同厚度的栅极介质（27，28）可在基板（21）来实现的半导体材料。存储单元阵列可特别地产生具有很少的工艺步骤和高堆积密度的硅衬底。所述存储器单元阵列和控制电路，用于读出在这里可以制备一体化。

4. 发明申请

WO1995031828A1 GAIN CELL DRAM STRUCTURE AND PROCESS FOR PRODUCING THE SAME 审中-公开
标题翻译：增益单元DRAM结构及其制造方法
公开(公告)号：WO1995031828A1
公开(公告)日：1995-11-23
申请号：PCT/EP1995001656
申请日：1995-05-02
申请人： SIEMENS AKTIENGESELLSCHAFT , KRAUTSCHNEIDER, Wolfgang , RISCH, Lothar , HOFMANN, Franz
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L27/108
CPC分类号： H01L27/10844 , H01L27/0629 , H01L27/108
摘要： An arrangement with dynamic MOS transistor gain memory cells has a selection transistor, a memory transistor and a diode structure. The selection transistor and the memory transistor are interconnected in series through a common node (20) and the diode structure (11) is connected between the common node and the gate electrode (10) of the memory transistor. In order to produce such an arrangement, the selection transistor and the memory transistor are realized as vertical MOS transistors. A vertical series of correspondingly doped zones (2, 3, 4) in which trenches (5, 6) are generated and which are provided with gate dielectric (7, 8) and gate electrode (9, 10) is further produced in particular by LPCVD epitaxy or by molecular-beam epitaxy. Insulating structures are formed by trenches (14, 17, 19).
摘要翻译：用于产生具有自放大动态MOS晶体管的存储单元的布置中，每一个都包括所述公共节点之间的选择晶体管，存储晶体管和一个二极管结构，其中通过共同的节点（20）的选择晶体管和存储晶体管串联连接，二极管结构（11）和所述栅电极（10）被连接在存储晶体管中，选择晶体管和存储晶体管实现为垂直MOS晶体管。为此（4×2，3）是特别LPCVD外延或由对应于在沟槽中产生掺杂区域的垂直序列（5，6）产生的分子束外延和栅极电介质（7，8）被提供并且栅极电极（10 9），通过沟槽（14，17，19）是绝缘的产生的结构。

5. 发明申请

WO1996033513A1 READ-ONLY STORAGE CELL ARRANGEMENT AND PROCESS FOR ITS PRODUCTION 审中-公开
标题翻译： HARD存储器单元装置和方法及其
公开(公告)号：WO1996033513A1
公开(公告)日：1996-10-24
申请号：PCT/DE1996000614
申请日：1996-04-09
申请人： SIEMENS AKTIENGESELLSCHAFT , HOFMANN, Franz , RISCH, Lothar , KRAUTSCHNEIDER, Wolfgang , RÖSNER, Wolfgang
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L27/112
CPC分类号： H01L27/11273 , H01L27/112
摘要： In a read-only storage cell arrangement with first storage cells comprising a vertical MOS transistor and second storage cells comprising no vertical MOS transistor, the storage cells are arranged along opposite sides of strip-like, parallel insulating trenches (16). The width and spacing of the insulating trenches (16) are preferably equal so that the storage cell arrangement can be made with 2F of space required per storage cell, in which F is the minimum structural size in the technology applied.
摘要翻译：在具有第一存储单元，其包括一垂直MOS晶体管，和第二存储单元，其不包含垂直MOS晶体管的只读存储单元结构中，沿着带形的，平行的隔离沟槽（16）的相对边缘上的存储器单元被布置。使得存储器单元阵列可以与用于2F <2>，的每个存储器单元，其中F是在相应的技术的最小特征尺寸的空间要求来实现的宽度和隔离沟槽（16）的间距优选是相等的。

6. 发明申请

WO1997002599A1 METHOD OF PRODUCING A READ-ONLY STORAGE CELL ARRANGEMENT 审中-公开
标题翻译：一种用于生产硬存储器单元装置
公开(公告)号：WO1997002599A1
公开(公告)日：1997-01-23
申请号：PCT/DE1996001117
申请日：1996-06-25
申请人： SIEMENS AKTIENGESELLSCHAFT , HOFMANN, Franz , RÖSNER, Wolfgang , KRAUTSCHNEIDER, Wolfgang , RISCH, Lothar
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L21/8247
CPC分类号： H01L27/11517 , H01L27/115
摘要： In order to produce a read-only storage cell arrangement, strip-shaped grooves are etched in a semiconductor substrate, storage cells each having a vertical MOS transistor with a floating gate (11) being formed on the flanks of these grooves. The source/drain areas of the MOS transistors are produced as strip-shaped doped areas at the base of the grooves (7) and between adjacent grooves (7) in a self-aligning manner using only one mask. The widths of the grooves (7) and the spacings between them are preferably identical such that the storage cell arrangement can be produced with a space requirement of 2F (F: minimum size of the structure).
摘要翻译：为了产生在半导体衬底中的只读存储单元阵列，条状蚀刻沟槽，在它们的边缘上形成各具有与浮置栅极（11）的垂直MOS晶体管的存储单元。所述MOS晶体管的源极/漏极区通过仅使用一个掩模制作在沟槽（7）的底部上的带状掺杂区域和相邻的沟槽（7）自对准方式之间。宽度和沟槽（7）的间距优选是相等的，使得具有2F的空间需求的存储单元阵列<2>：是可实现的（F最小特征尺寸）。

7. 发明申请

WO1996013064A1 PROCESS FOR PRODUCING A READ-ONLY STORAGE CELL ARRANGEMENT WITH VERTICAL MOS TRANSISTORS 审中-公开
标题翻译：方法用于生产具有垂直MOS晶体管的一道存储器单元装置
公开(公告)号：WO1996013064A1
公开(公告)日：1996-05-02
申请号：PCT/DE1995001365
申请日：1995-10-05
申请人： SIEMENS AKTIENGESELLSCHAFT , RISCH, Lothar , HOFMANN, Franz , RÖSNER, Wolfgang , KRAUTSCHNEIDER, Wolfgang
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L21/8246
CPC分类号： H01L27/112
摘要： To produce a read-only storage cell arrangement with first storage cells comprising a vertical MOS transistor and second storage cells comprising no vertical MOS transistors, holes (13) are etched in a silicon substrate (1) with a sequence of layers corresponding to source (1), channel (2) and drain (11) for the first storage cells, having a gate dielectric (14) and a gate electrode (15a). Insulation pits (7) at a spacing of preferably their width are produced to isolate neighbouring storage cells.
摘要翻译：为了生产具有包括垂直MOS晶体管的第一存储单元不包括垂直MOS晶体管的只读存储单元结构中，和第二存储单元根据所述源（1），通道（2）和漏区是在硅衬底（1）的层序列被提供（11）蚀刻（13），用于与栅极电介质（14）和栅电极（15A）的第一存储器单元孔。对于（7），产生相邻的存储器单元的绝缘沟槽隔离，该距离优选地等于其宽度。

8. 发明申请

WO1998011604A1 METHOD FOR PRODUCING A DRAM CELLULAR ARRANGEMENT 审中-公开
标题翻译：一种用于生产DRAM单元安排
公开(公告)号：WO1998011604A1
公开(公告)日：1998-03-19
申请号：PCT/DE1997001580
申请日：1997-07-28
申请人： SIEMENS AKTIENGESELLSCHAFT , RÖSNER, Wolfgang , RISCH, Lothar , HOFMANN, Franz , STENGL, Reinhard
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The invention concerns a DRAM cellular arrangement comprising a vertical MOS transistor in every memory cell. The first source/drain area (4) of said transistor is connected to a storage node of a memory condenser (4, 15, 16), the channel area (3) of which is surrounded annularly by a gate electrode (13). The second source/drain area of the channel area is connected to a buried bit line (2). The DRAM cellular arrangement is produced by using only two masks assisted by a spacer with a memory cell surface of 2F , whereby F represents the minimum structural size that the relevant technology can produce.
摘要翻译：包括用于每个存储单元包括一垂直MOS晶体管，它的第一源极DRAM单元排列区/漏区（4），以一个存储电容器的存储节点（4，15，16）连接到它的沟道区（3）环形地由一个栅电极（13）被封闭并且具有埋入式位线的第二源极/漏极区域（2）。 DRAM单元布置仅使用两个使用间隔物技术与2F <2>，的存储单元面积，其中F是在各自的技术特征尺寸的最小可制造掩模制造。

9. 发明申请

WO1997044826A1 DRAM CELL ARRAY AND METHOD OF MANUFACTURING IT 审中-公开
标题翻译： DRAM单元安排和方法及其
公开(公告)号：WO1997044826A1
公开(公告)日：1997-11-27
申请号：PCT/DE1997000812
申请日：1997-04-23
申请人： SIEMENS AKTIENGESELLSCHAFT , RISCH, Lothar , HOFMANN, Franz , RÖSNER, Wolfgang , ÄUGLE, Thomas
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L27/108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A DRAM cell array has storage cells integrated in a semiconductor substrate (1), each of which has a storage capacitor (7, 8, 9, 11), and a vertical MOS transistor (11, 14a, 14b, 17, 28) located above that. The storage capacitor is located in a trench (6). Between each two trenches (6), which are surrounded by an insulating structure (12, 13), a semiconductor island (14) is located, on whose flanks the vertical MOS transistors are implemented. With the help of self-adjusting process steps, the DRAM cell array can be produced both in open-bitline and in folded-bitline architecture, with a space requirement per storage cell of 4F (where F is the minimum structure size that can be manufactured in the respective technology).
摘要翻译：该DRAM单元阵列集成每一个都具有一个存储电容器（7，8，9，11）的存储单元和一个上方的半导体衬底（1），其设置垂直MOS晶体管（11，14A，14B，17，28）。存储电容器被布置在沟槽（6）。每一对沟槽（6），其是绝缘结构（12，13）所包围的的之间，设置在半导体岛（14），在其边缘垂直MOS晶体管实现。用的自对准工艺步骤的帮助下，DRAM单元布置是二者开路位线，并与每4F的存储单元中的空间需求折叠位线结构<2>：制造（F最小在相应Technolgie结构尺寸制造的）。

10. 发明申请

WO1993016490A1 METHOD OF PRODUCING A CONTACT WITH A TRENCH-CONDENSER ELECTRODE 审中-公开
标题翻译：生产与TRENCH-CONDENSER电极接触的方法
公开(公告)号：WO1993016490A1
公开(公告)日：1993-08-19
申请号：PCT/DE1993000078
申请日：1993-02-01
申请人： SIEMENS AKTIENGESELLSCHAFT , RÖSNER, Wolfgang , HOFMANN, Franz , RISCH, Lothar
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L21/82
CPC分类号： H01L27/10861 , H01L27/10829
摘要： In order to produce a contact between a condenser electrode (13) located in a trench (11) and an MOS-transistor source/drain region located outside the trench, the invention calls for the trench (11) to be produced by making a shallow etch in the substrate (1), trued with respect to the field oxide region which insulates the MOS transistor. After forming an Si3N4 spacer (10) on the substrate wall (8) exposed by the silicon-selective etching operation, the exposed part of the field oxide region (2) is first removed using a mask, and then the trench (11) completed by means of a further etching operation. The contact is produced by formation of an SiO2 film (12) on the surface of the trench (11), removal of the Si3N4 spacer (10) and formation of the condenser electrode (13) on the substrate wall (8) exposed by removal of the Si3N4 spacer (10).

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