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11. 发明申请

US20220221986A1 FABRIC MEMORY NETWORK-ON-CHIP 有权
公开(公告)号：US20220221986A1
公开(公告)日：2022-07-14
申请号：US17711840
申请日：2022-04-01
申请人： Scott Jeremy Weber , Ashish Gupta , Navid Azizi , Ilya K. Ganusov , Kalen Brunham , Przemek Guzy , Rajiv Kumar , Thuyet Ngo , Mark Honman
发明人： Scott Jeremy Weber , Ashish Gupta , Navid Azizi , Ilya K. Ganusov , Kalen Brunham , Przemek Guzy , Rajiv Kumar , Thuyet Ngo , Mark Honman
IPC分类号： G06F3/06
摘要： An integrated circuit device includes a programmable fabric that has a plurality of memory blocks. The integrated circuit device also includes a network-on-chip (NOC) located on a shoreline of the programmable fabric and at least one micro NOC formed with hardened resources in the programmable fabric. The at least one micro NOC is communicatively coupled to the NOC and to at least one memory block of the plurality of memory blocks. Additionally, the at least one micro NOC is configurable to route data between the NOC and the at least one memory block.

12. 发明授权

US08627254B2 Method and apparatus for simultaneous switching noise optimization 有权
标题翻译：用于同时开关噪声优化的方法和装置
公开(公告)号：US08627254B2
公开(公告)日：2014-01-07
申请号：US13618176
申请日：2012-09-14
申请人： Michael Howard Kipper , Joshua David Fender , Navid Azizi , David Samuel Goldman
发明人： Michael Howard Kipper , Joshua David Fender , Navid Azizi , David Samuel Goldman
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5054 , G06F17/5077 , G06F2217/82
摘要： Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value. The minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block are determined such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin.
摘要翻译：介绍了利用计算机辅助设计（CAD）工具设计的集成电路（IC）中降低同时开关噪声（SSN）的方法和装置。在一种方法中，CAD工具接收到IC参数的值分配。值分配作为一个值范围输入。确定I / O块中每个输入/输出（I / O）引脚的最小和最大路径延迟，使得满足接收到的值分配。 I / O引脚的实际切换时间及时扩展，以降低I / O引脚中的SSN。切换时间被分散，以使切换时间落在对应的I / O引脚的最小和最大路径延迟之间。

13. 发明申请

US20130080987A1 METHOD AND APPARATUS FOR SIMULTANEOUS SWITCHING NOISE OPTIMIZATION 有权
标题翻译：同时开关噪声优化的方法与装置
公开(公告)号：US20130080987A1
公开(公告)日：2013-03-28
申请号：US13618176
申请日：2012-09-14
申请人： Michael Howard Kipper , Joshua David Fender , Navid Azizi , David Samuel Goldman
发明人： Michael Howard Kipper , Joshua David Fender , Navid Azizi , David Samuel Goldman
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5054 , G06F17/5077 , G06F2217/82
摘要： Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value. The minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block are determined such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin.
摘要翻译：介绍了利用计算机辅助设计（CAD）工具设计的集成电路（IC）中降低同时开关噪声（SSN）的方法和装置。在一种方法中，CAD工具接收到IC参数的值分配。值分配作为一个值范围输入。确定I / O块中每个输入/输出（I / O）引脚的最小和最大路径延迟，使得满足接收到的值分配。 I / O引脚的实际切换时间及时扩展，以降低I / O引脚中的SSN。切换时间被分散，以使切换时间落在对应的I / O引脚的最小和最大路径延迟之间。

14. 发明授权

US08302058B1 Reducing simultaneous switching noise in an integrated circuit design during placement 有权
标题翻译：放置期间降低集成电路设计中的同时开关噪声
公开(公告)号：US08302058B1
公开(公告)日：2012-10-30
申请号：US12557798
申请日：2009-09-11
申请人： Michael Howard Kipper , Joshua David Fender , Navid Azizi
发明人： Michael Howard Kipper , Joshua David Fender , Navid Azizi
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/82
摘要： Methods, computer programs, and Integrated Circuits (IC) for minimizing Simultaneous Switching Noise (SSN) in the design of an IC are presented. In one embodiment, the method includes moving a candidate pin of the IC in an initial input/output (I/O) layout to create a candidate I/O layout. Further, in one operation the method calculates a first performance cost for the initial I/O layout and a second performance cost for the candidate I/O layout. The first and the second performance costs are based on an SSN cost for the initial layout and on an SSN cost for the candidate layout respectively. The method selects the layout to design the IC that has the lowest performance cost. The method operations are performed during the placement phase of an IC Computer Aided Design (CAD) tool.
摘要翻译：提出了一种用于最小化IC设计中同时开关噪声（SSN）的方法，计算机程序和集成电路（IC）。在一个实施例中，该方法包括在初始输入/输出（I / O）布局中移动IC的候选引脚以创建候选I / O布局。此外，在一个操作中，该方法计算初始I / O布局的第一性能成本和候选I / O布局的第二性能成本。第一和第二个性能成本分别基于初始布局的SSN成本和候选布局的SSN成本。该方法选择布局来设计具有最低性能成本的IC。方法操作在IC计算机辅助设计（CAD）工具的放置阶段执行。

15. 发明授权

US08151233B1 Circuit design with incremental simultaneous switching noise analysis 有权
标题翻译：电路设计采用增量同时开关噪声分析
公开(公告)号：US08151233B1
公开(公告)日：2012-04-03
申请号：US12419518
申请日：2009-04-07
申请人： Navid Azizi , Joshua David Fender
发明人： Navid Azizi , Joshua David Fender
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5081 , G06F2217/82
摘要： Methods, computer programs, and systems for designing an electronic component are presented. One method calculates a first Simultaneous Switching Noise (SSN) on Input/Output (IO) pins using a first configuration of the electronic component. A setting or a placement of a chosen IO pin is changed to obtain a second configuration of the electronic component, and a second SSN on IO pins is obtained based on the results of the first SSN and based on new SSN calculations related to the changed setting or placement. The second SSN on an IO pin, other than the chosen IO pin, is calculated by subtracting from the first SSN on the IO pin the SSN caused by the chosen IO pin calculated in the first SSN, and by adding an incremental SSN caused by the chosen IO pin on the pin in the second configuration. The method further includes the operation of creating a design for the electronic component with either the first or the second configuration based on the results of the first and the second SSN.
摘要翻译：介绍了设计电子元件的方法，计算机程序和系统。一种方法使用电子元件的第一配置计算输入/输出（IO）引脚上的第一同步开关噪声（SSN）。改变所选IO引脚的设置或放置以获得电子部件的第二配置，并且基于第一SSN的结果并且基于与改变的设置相关的新的SSN计算来获得IO引脚上的第二SSN 或放置。通过从IO引脚上的第一个SSN中减去由第一个SSN中计算的所选IO引脚引起的SSN，并通过添加由该引脚引起的增量SSN来计算IO引脚上的第二个SSN 在第二个配置中，在引脚上选择IO引脚。该方法还包括基于第一和第二SSN的结果，利用第一或第二配置为电子部件创建设计的操作。

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