专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08296704B1 Method and apparatus for simultaneous switching noise optimization 有权
标题翻译：用于同时开关噪声优化的方法和装置
公开(公告)号：US08296704B1
公开(公告)日：2012-10-23
申请号：US12833797
申请日：2010-07-09
申请人： Michael Howard Kipper , Joshua David Fender , Navid Azizi , David Samuel Goldman
发明人： Michael Howard Kipper , Joshua David Fender , Navid Azizi , David Samuel Goldman
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5054 , G06F17/5077 , G06F2217/82
摘要： Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value assignments or as a list of possible value assignments. Further, the method includes an operation for determining the minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin. Additionally, other method operations are included for routing paths to the I/O pins to meet the actual switching times and for creating a design for the IC that meets the actual switching times.
摘要翻译：介绍了利用计算机辅助设计（CAD）工具设计的集成电路（IC）中降低同时开关噪声（SSN）的方法和装置。在一种方法中，CAD工具接收到IC参数的值分配。值分配作为值分配的范围输入，或作为可能的值分配列表。此外，该方法包括用于确定I / O块中的每个输入/输出（I / O）引脚的最小和最大路径延迟的操作，使得满足接收的值分配。 I / O引脚的实际切换时间及时扩展，以降低I / O引脚中的SSN。切换时间被分散，以使切换时间落在对应的I / O引脚的最小和最大路径延迟之间。此外，还包括其他方法操作，用于路由到I / O引脚的路径，以满足实际切换时间，并为IC创建满足实际切换时间的设计。

2. 发明授权

US08627254B2 Method and apparatus for simultaneous switching noise optimization 有权
标题翻译：用于同时开关噪声优化的方法和装置
公开(公告)号：US08627254B2
公开(公告)日：2014-01-07
申请号：US13618176
申请日：2012-09-14
申请人： Michael Howard Kipper , Joshua David Fender , Navid Azizi , David Samuel Goldman
发明人： Michael Howard Kipper , Joshua David Fender , Navid Azizi , David Samuel Goldman
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5054 , G06F17/5077 , G06F2217/82
摘要： Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value. The minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block are determined such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin.
摘要翻译：介绍了利用计算机辅助设计（CAD）工具设计的集成电路（IC）中降低同时开关噪声（SSN）的方法和装置。在一种方法中，CAD工具接收到IC参数的值分配。值分配作为一个值范围输入。确定I / O块中每个输入/输出（I / O）引脚的最小和最大路径延迟，使得满足接收到的值分配。 I / O引脚的实际切换时间及时扩展，以降低I / O引脚中的SSN。切换时间被分散，以使切换时间落在对应的I / O引脚的最小和最大路径延迟之间。

3. 发明申请

US20130080987A1 METHOD AND APPARATUS FOR SIMULTANEOUS SWITCHING NOISE OPTIMIZATION 有权
标题翻译：同时开关噪声优化的方法与装置
公开(公告)号：US20130080987A1
公开(公告)日：2013-03-28
申请号：US13618176
申请日：2012-09-14
申请人： Michael Howard Kipper , Joshua David Fender , Navid Azizi , David Samuel Goldman
发明人： Michael Howard Kipper , Joshua David Fender , Navid Azizi , David Samuel Goldman
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5054 , G06F17/5077 , G06F2217/82
摘要： Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value. The minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block are determined such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin.
摘要翻译：介绍了利用计算机辅助设计（CAD）工具设计的集成电路（IC）中降低同时开关噪声（SSN）的方法和装置。在一种方法中，CAD工具接收到IC参数的值分配。值分配作为一个值范围输入。确定I / O块中每个输入/输出（I / O）引脚的最小和最大路径延迟，使得满足接收到的值分配。 I / O引脚的实际切换时间及时扩展，以降低I / O引脚中的SSN。切换时间被分散，以使切换时间落在对应的I / O引脚的最小和最大路径延迟之间。

4. 发明授权

US08302058B1 Reducing simultaneous switching noise in an integrated circuit design during placement 有权
标题翻译：放置期间降低集成电路设计中的同时开关噪声
公开(公告)号：US08302058B1
公开(公告)日：2012-10-30
申请号：US12557798
申请日：2009-09-11
申请人： Michael Howard Kipper , Joshua David Fender , Navid Azizi
发明人： Michael Howard Kipper , Joshua David Fender , Navid Azizi
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/82
摘要： Methods, computer programs, and Integrated Circuits (IC) for minimizing Simultaneous Switching Noise (SSN) in the design of an IC are presented. In one embodiment, the method includes moving a candidate pin of the IC in an initial input/output (I/O) layout to create a candidate I/O layout. Further, in one operation the method calculates a first performance cost for the initial I/O layout and a second performance cost for the candidate I/O layout. The first and the second performance costs are based on an SSN cost for the initial layout and on an SSN cost for the candidate layout respectively. The method selects the layout to design the IC that has the lowest performance cost. The method operations are performed during the placement phase of an IC Computer Aided Design (CAD) tool.
摘要翻译：提出了一种用于最小化IC设计中同时开关噪声（SSN）的方法，计算机程序和集成电路（IC）。在一个实施例中，该方法包括在初始输入/输出（I / O）布局中移动IC的候选引脚以创建候选I / O布局。此外，在一个操作中，该方法计算初始I / O布局的第一性能成本和候选I / O布局的第二性能成本。第一和第二个性能成本分别基于初始布局的SSN成本和候选布局的SSN成本。该方法选择布局来设计具有最低性能成本的IC。方法操作在IC计算机辅助设计（CAD）工具的放置阶段执行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式