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1. 发明申请

US20220221986A1 FABRIC MEMORY NETWORK-ON-CHIP 有权
公开(公告)号：US20220221986A1
公开(公告)日：2022-07-14
申请号：US17711840
申请日：2022-04-01
申请人： Scott Jeremy Weber , Ashish Gupta , Navid Azizi , Ilya K. Ganusov , Kalen Brunham , Przemek Guzy , Rajiv Kumar , Thuyet Ngo , Mark Honman
发明人： Scott Jeremy Weber , Ashish Gupta , Navid Azizi , Ilya K. Ganusov , Kalen Brunham , Przemek Guzy , Rajiv Kumar , Thuyet Ngo , Mark Honman
IPC分类号： G06F3/06
摘要： An integrated circuit device includes a programmable fabric that has a plurality of memory blocks. The integrated circuit device also includes a network-on-chip (NOC) located on a shoreline of the programmable fabric and at least one micro NOC formed with hardened resources in the programmable fabric. The at least one micro NOC is communicatively coupled to the NOC and to at least one memory block of the plurality of memory blocks. Additionally, the at least one micro NOC is configurable to route data between the NOC and the at least one memory block.

2. 发明申请

US20120110400A1 Method and Apparatus for Performing Memory Interface Calibration 审中-公开
标题翻译：执行存储器接口校准的方法和装置
公开(公告)号：US20120110400A1
公开(公告)日：2012-05-03
申请号：US12959666
申请日：2010-12-03
申请人： Valavan Manohararajah , Ivan Bluno , Przemek Guzy , Kalen B. Brunham
发明人： Valavan Manohararajah , Ivan Bluno , Przemek Guzy , Kalen B. Brunham
IPC分类号： G11C29/00 , G11C7/00 , G06F11/16
CPC分类号： G11C29/028 , G11C7/10 , G11C29/022 , G11C29/023
摘要： A universal memory interface on an integrated circuit includes an external memory interface unit operable to perform data rate conversion for a data signal between a first rate associated with the integrated circuit and a second rate associated with a memory system. The universal memory interface also includes a sequencer unit operable to calibrate at least one of a delay for the data signal and a delay for a strobe for the data signal by executing a calibration procedure instruction.
摘要翻译：集成电路上的通用存储器接口包括外部存储器接口单元，其可操作以对与集成电路相关联的第一速率与与存储器系统相关联的第二速率之间的数据信号执行数据速率转换。通用存储器接口还包括定序器单元，用于通过执行校准程序指令来校准数据信号的延迟和数据信号的选通脉冲的延迟中的至少一个。

3. 发明授权

US08661329B1 Generation of readable hierarchical path identifiers 有权
标题翻译：生成可读分层路径标识符
公开(公告)号：US08661329B1
公开(公告)日：2014-02-25
申请号：US12732110
申请日：2010-03-25
申请人： Mark Ari Teper , Przemek Guzy , Steven Caranci
发明人： Mark Ari Teper , Przemek Guzy , Steven Caranci
IPC分类号： G06F3/00
CPC分类号： G06F17/5045
摘要： A system evaluates a hierarchical name set such as names produced by hardware descriptor language (HDL) synthesis and generates shorter, unambiguous names for each of the hierarchical names in the name set. A directed graph and/or a tree is generated using a hierarchical name set. Each name is evaluated using the directed graph and/or tree to identify hierarchical components or tokens of the name required in the short name. Name length can be reduced even in a system having large numbers of common hierarchies.
摘要翻译：系统评估诸如由硬件描述符语言（HDL）合成产生的名称的分层名称集合，并为名称集中的每个分层名称生成更短，明确的名称。使用分层名称集生成有向图和/或树。使用有向图和/或树来评估每个名称，以标识短名称中所要求的名称的分层组件或令牌。即使在具有大量共同层次结构的系统中，也可以减少名称长度。

4. 发明申请

US20080216034A1 Performance Visualization of Delay in Circuit Design 失效
标题翻译：电路设计延迟的性能可视化
公开(公告)号：US20080216034A1
公开(公告)日：2008-09-04
申请号：US12101088
申请日：2008-04-10
申请人： Przemek Guzy , Steven Caranci
发明人： Przemek Guzy , Steven Caranci
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Methods are provided for presenting delay characteristics of a circuit design. The methods acquire routing delay data and logic delay data for each of a number of paths within the circuit design. In one method, a scatterplot of the routing delay data versus the logic delay data for each of the paths is generated and rendered. In another method, the paths are specified as being associated with modules within the circuit design. In this method, a histogram plot of the paths within each module is generated, wherein the paths within each module are identified as being dominated by routing delay or logic delay. In another embodiment, a connectivity diagram is generated to convey an amount of connectivity within modules and between modules. Each of the methods can be implemented as program instructions on a computer readable medium.
摘要翻译：提供了用于呈现电路设计的延迟特性的方法。该方法为电路设计中的多个路径中的每一个获取路由延迟数据和逻辑延迟数据。在一种方法中，生成并渲染路由延迟数据与每个路径的逻辑延迟数据的散点图。在另一种方法中，将路径指定为与电路设计中的模块相关联。在该方法中，生成每个模块内的路径的直方图，其中每个模块内的路径被识别为由路由延迟或逻辑延迟支配。在另一个实施例中，生成连接图以传送模块内和模块之间的连接量。每个方法可以被实现为计算机可读介质上的程序指令。

5. 发明授权

US08443334B1 Method and apparatus for generating graphical representations of slack potential for slack paths 有权
标题翻译：用于产生松弛路径的松弛电位的图形表示的方法和装置
公开(公告)号：US08443334B1
公开(公告)日：2013-05-14
申请号：US13396662
申请日：2012-02-15
申请人： Przemek Guzy
发明人： Przemek Guzy
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/84
摘要： A method for designing a system to be implemented on a target device includes computing slack potential of paths between components on the target device after timing analysis. A graphical representation of the slack potential and slack for the paths is generated. The graphical representation identifies that a design change is required for a first portion of the system associated with a first path and that a change in placement is required for a second portion of the system associated with the second path.
摘要翻译：用于设计要在目标设备上实现的系统的方法包括在定时分析之后计算目标设备上的组件之间的路径的松弛潜力。生成路径的松弛电位和松弛的图形表示。图形表示标识出与第一路径相关联的系统的第一部分需要设计改变，并且对于与第二路径相关联的系统的第二部分需要改变放置。

6. 发明授权

US08141018B1 Method and apparatus for using slack potential data to design a system on a field programmable gate array 有权
标题翻译：用于使用松弛势数据来设计现场可编程门阵列上的系统的方法和装置
公开(公告)号：US08141018B1
公开(公告)日：2012-03-20
申请号：US12319954
申请日：2009-01-14
申请人： Przemek Guzy
发明人： Przemek Guzy
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/84
摘要： A method for designing a system to be implemented on a target device includes computing slack potential of paths between components on the target device after timing analysis. A graphical representation of the slack potential and slack for the paths is generated. The graphical representation identifies that a design change is required for a first portion of the system associated with a first path and that a change in placement is required for a second portion of the system associated with the second path.
摘要翻译：用于设计要在目标设备上实现的系统的方法包括在定时分析之后计算目标设备上的组件之间的路径的松弛潜力。生成路径的松弛电位和松弛的图形表示。图形表示标识出与第一路径相关联的系统的第一部分需要设计改变，并且对于与第二路径相关联的系统的第二部分需要改变放置。

7. 发明授权

US07657857B2 Performance visualization of delay in circuit design 失效
标题翻译：电路设计延迟的性能可视化
公开(公告)号：US07657857B2
公开(公告)日：2010-02-02
申请号：US12101088
申请日：2008-04-10
申请人： Przemek Guzy , Steven Caranci
发明人： Przemek Guzy , Steven Caranci
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Methods are provided for presenting delay characteristics of a circuit design. The methods acquire routing delay data and logic delay data for each of a number of paths within the circuit design. In one method, a scatterplot of the routing delay data versus the logic delay data for each of the paths is generated and rendered. In another method, the paths are specified as being associated with modules within the circuit design. In this method, a histogram plot of the paths within each module is generated, wherein the paths within each module are identified as being dominated by routing delay or logic delay. In another embodiment, a connectivity diagram is generated to convey an amount of connectivity within modules and between modules. Each of the methods can be implemented as program instructions on a computer readable medium.
摘要翻译：提供了用于呈现电路设计的延迟特性的方法。该方法为电路设计中的多个路径中的每一个获取路由延迟数据和逻辑延迟数据。在一种方法中，生成并渲染路由延迟数据与每个路径的逻辑延迟数据的散点图。在另一种方法中，将路径指定为与电路设计中的模块相关联。在该方法中，生成每个模块内的路径的直方图，其中每个模块内的路径被识别为由路由延迟或逻辑延迟支配。在另一个实施例中，生成连接图以传送模块内和模块之间的连接量。每个方法可以被实现为计算机可读介质上的程序指令。

8. 发明授权

US07197734B1 Method and apparatus for designing systems using logic regions 有权
标题翻译：用于设计使用逻辑区域的系统的方法和装置
公开(公告)号：US07197734B1
公开(公告)日：2007-03-27
申请号：US10194199
申请日：2002-07-12
申请人： Deshanand P. Singh , Terry P. Borer , Steven Caranci , Tim Vanderhoek , Ivan Hamer , Jimmy Kuo , Przemek Guzy , Alexander Grbic , Rebecca Katzin , Stephen D. Brown , Zvonko Vranesic
发明人： Deshanand P. Singh , Terry P. Borer , Steven Caranci , Tim Vanderhoek , Ivan Hamer , Jimmy Kuo , Przemek Guzy , Alexander Grbic , Rebecca Katzin , Stephen D. Brown , Zvonko Vranesic
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/08
摘要： A method for positioning components of a system onto a target device utilizing programmable logic devices (PLDs) is disclosed. A first location on the target device for a first logic region having a first component is determined. Determined properties of the first logic region are preserved. The first logic region is integrated with a second logic region having a second component in view of the determined properties.
摘要翻译：公开了一种使用可编程逻辑器件（PLD）将系统的组件定位到目标器件上的方法。确定具有第一分量的第一逻辑区域的目标设备上的第一位置。确定第一逻辑区域的确定的属性。鉴于所确定的属性，第一逻辑区域与具有第二分量的第二逻辑区域集成。

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